VP9 Parallel Pipelined Decoder And Its Network-on-chip Design

In 2013,the world's leading company Google launched a new generation of video codec VP9.Once VP9 video codec has been launched,it has received wide attention in the industry.More and more vendors begin to support VP9,and digital video using VP9 video coding technology has become a big part of the online video in foreign countries.As an alternative to the traditional bus on chip system architecture,the network-on-chip(NoC)is the hotspot of current system on chip design,and has been widely used in the design of multi-core systems.In this paper,VP9 encoding and decoding technology and network-on-chip technology are studied in depth.A VP9 parallel pipelined decoder is designed by improving the VP9 decoder,and the network-on-chip is designed for the decoder.The main work of this paper is as follows:(1)The design of VP9 parallel pipelined decoder.Firstly,the VP9 decoding process is analyzed.According to the data flow characteristics of entropy decoding,inverse quantization and inverse transform,intra prediction,motion compensation,loop deblocking filter module and the calculation of each module,we proposed a parallel pipelined VP9 decoding method to optimize VP9 decoder.And MPI parallel library is used to modify the libvpx source code to complete the software implementation of the decoder,and experiment has been performed to verify its function and measure its decoding acceleration ratio.(2)Network-on-chip design of VP9 parallel pipelined decoder.In this paper,2D-Mesh is chosen as the network-on-chip topology,and wormhole switching is chosen as the network-on-chip switching mechanism and XY routing strategy are adopted.In the design process,a low latency mapping algorithm based on pipelined application is proposed in this paper to reduce the communication delay of network-on-chip.The VP9 parallel pipelined decoder is mapped onto an network-on-chip using the proposed algorithm.The whole system simulation platform Gem5 is used to simulate the system,and the decoding acceleration ratio of the network-on-chip is compared under different mapping schemes.The experiment shows that the parallel pipelined VP9 decoder's decoding acceleration ratio can reach 5.21 when decoding 1920x1080 resolution videos,it can be used forhigh-speed real-time decoding and greatly improves the decoding speed of the decoder.The network-on-chip of the VP9 parallel pipelined decoder designed in this paper can realize the decoding function fully,and the communication delay of the chip network is smaller in this mapping scheme.