Design And Implementation Of Vector Error Diffusion Algorithm IP Core Based On FPGA

In the printing system,digital halftone technique is one of the key technologies which directly affect the print results.The error diffusion algorithm has become one of the most widely used digital halftone algorithms due to its superiority in halftone results and performance.However,there are many drawbacks of the traditional error diffusion algorithm applied to color image processing: on the one hand,it carries on the error diffusion processing to the data information of each color channel independently,and ignores the correlation between different color channels.So the quality of the halftone image is poor.The vector error diffusion algorithm was proposed to solve the problem,which uses the vector calculation method to deal with the color information of different color channels,retains the correlation between the color channels,and get better halftone results;On the other hand,the existing algorithm is mainly based on PC platform implementation,the whole process adopts serial execution method,not only can’t meet the requirement of real-time printing system,but also increased the dependence of the printing system on PC,and limits the offline operation of printing system;At the same time,with the rapid development of FPGA technology provide the basis for the offline printing of the printing system.Therefore,the research on implementation of vector error diffusion algorithm based on FPGA has great significance.This thesis analyzes the feasibility of implementing vector error diffusion algorithm on FPGA platform,and designs and realizes key technology.Our contribution is as follows:1.Research on parallel operation of multi-color channels.The process of vector error diffusion algorithm is decomposed into some modules,and the pre-memory is designed so that the error search module which needs to be run synchronously can also run in parallel,thus realizing the parallelization of multi-color channels.2.Multi-channel error diffusion.This thesis design error diffusion value search,and uses the optimal error coefficient matrix Linearized CIELab to replace the traditional FloydSteinberg matrix,and makes the diffusion diffuse between multi-channel perfectly.3.Error value generation optimization.This thesis use the extended register as the sign bit to extend the unsigned operation to the signed operation in Verilog.At the same time,we design the diffusion coefficient pre-memory to replace the multiplication of algorithm,which improve performance of algorithm.4.System pipelining design.The flow structure of the pipeline is designed,which reduces the running time and improves the parallelism and throughput of systemFinnally,the algorithm is encapsulated into a reusable IP kernel,and the IP core verification system is designed with So CKit development board.The experimental results show that the halftone results of vector error diffusion algorithm based on FPGA are basically same with the result of Matlab,and have great advantage in speed.In the premise of ensuring halftone results,it not only satisfies the real-time requirement of printing system,but also provides the basis for offline operation for the printing system.