The IP Core Design Of Error Diffusion Algorithm And The Implementation Of Halftone System Based On SOPC

Digital halftoning is one of the key technologies of the printing system, directlydetermines the quality of output image, so its position in the printing system is veryimportant. The commonly used halftone algorithm include threshold dithering methodand error diffusion method. Error diffusion method is superior to threshold ditheringmethod, however, because its large computation, so must rely on high-speed PCprocessor and mass storage devices to meet the requirements of real-time, which greatlylimits the scope of its application.In this thesis, the IP core design of digital halftone algorithms and theimplementation of embedded systems were studied. First, the two halftone algorithmmentioned above are analyzed and compared; secondly, analyzing the characteristics ofthe implementation of error diffusion method, using LUT(look-up table) and theassembly line method to improve it on FPGA, the error diffusion module cost only oneclock cycle to calculate a result of the halftone pixel in average, greatly enhancing theefficiency of a halftone; last，the minimum halftone system is constructed in use ofSOPC technology. This paper analyzes the Avalon bus signals and timing characteristics,and use the Avalon memory-mapped interface to package the error diffusion module.Finally，the source image data in the memory were sent into the error diffusion modulethrough the Avalon bus and the halftone values can be obtained directly.