Research Of Multi-core Interconnection Networks For Image Processing

The continuous progress of wireless communication technology and the arrival of the 4G era,consumers' demand for multimedia is increasingly urgent.The effective compression of multimedia data has become a very challenging and hot topic.The large scale computation in the video coding process introduces more demanding performance requirements for processors that support real-time image processing.Networks-on-Chip(No C)becomes the first choice for future System-on-Chip architecture and the future development direction of multi-core systems for image processing applications.Networks-on-Chip for image processing applications requires good architecture support,so it is important to study the No C interconnect architecture for image processing applications to achieve more efficient image and video processing.In this thesis,the previous research of No C interconnection architecture for video processing are summarized,and the interconnection architecture of HEVC video coding application is also studied.The main achievements of this thesis are as follows:1.The existing multi-core video processing architecture usually uses 2D No C technology for core interconnection,that makes the number of the interconnected cores small and limits the computing ability.The thesis presents an interconnection architecture using optoelectronic mixing transmission,fusion switching scheme and dynamic application assignment.This architecture uses function block parallel to implement HEVC high-definition video coding by multi cores.A variety of switching mechanisms and photoelectric hybrid transmission are introduced for the multi-granularity,high bandwidth and low delay feature of video coding traffic.The simulator based on OPNET is also developed to analyzes the performance of the architecture,and the simulation results show that the proposed architecture achieves a better network performance,as it improved the average throughput for about 32.1% compared to 2D-Mesh architecture.2.The video processing architecture with function block parallel is faced with the complexity difference between different modules,poor scalability and high demand for inter-core communication.This thesis presents a video processing architecture that uses data parallelism.The architecture uses the data parallel method to divide the video data into several parts and each part is encoded by different independent core.The proposed architecture effectively reduces the inter-core communication demands,balances the computing load of each core,makes full use of the on-chip computing resources,and have better portability.Cluster-based architecture is applied in the Tile-level video parallel processing to achieve multi-level B frame coding.By using the design of shared cache,the architecture reduces the amount of communication between cores and achieves high-speed sharing of inter prediction data.The optical bus is used in storage layer to achieve high bandwidth and low latency communication between off-chip storage and the on-chip storage.Compared with the 3D-Mesh on-chip network architecture,which uses data parallelism and function parallel mode respectively,the results show that the proposed architecture improves the throughput for 124.7% and 27.78% respectively.