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Design And Verification Of RSA/SM2 Logic Component Oriented To Modular Optimization

Posted on:2018-10-25Degree:MasterType:Thesis
Country:ChinaCandidate:J R ZhuFull Text:PDF
GTID:2348330518988601Subject:Computer system architecture
Abstract/Summary:
With the continuous development of information technology,network security has got more and more attention.Cryptography provides a strong support for information security.In particular,the public key cryptography represented by RSA and ECC solves the critical issues such as key distribution and identity recognition of symmetric cryptography.In order to improve the efficiency and security of the public key cryptography algorithm,the related cipher coprocessor and chiper chips integrate the cryptography algorithms into the circuit design,and the complex operation of modular multiplication,modular exponentiation and modular inverse in the algorithms is realized by hardware.Based on the research of modular multiplication algorithm,we analyze the advantages of Montgomery modular multiplication.The modular multiplication is optimized by making full use of the correlation of the data in the case of equal operands.The arithmetic circuit is designed by hardware description language and the modular multiplication and modular exponentiation are realized by FPGA.The main research work and innovation are as follows:1.A dual-field efficient modular multiplication algorithm based on FIPS algorithm is proposed.The algorithm takes full account of the modular multiplication algorithm of the public key cryptography in the case of equal operands,which reduces the redundant operations such as multiplication,addition,and read.It improves the efficiency of the modular multiplication and reduces the computational power consumption,and provides a unified dual-field modular multiplication for the RSA and SM2 algorithms in resource constrained devices.2.A scalable dual-field modular multipler circuit in Verilog HDL is designed.The circuit is composed of pipelining structure and focuses on small area and low power consumption,including dual-field multiplier,dual-field adder and modular multiplication control state machine to realize the control of the key data path.The circuit is implemented on FPGA to verify the effectiveness and it provides an important reference for the application of public key cryptography in resource constrained devices.3.The hardware circuit design of modular exponentiation with Montgomery modular multiplication is analyzed.By instantiating the modular multiplication module designed in the paper,we compare the features and advantages of each modular exponentiation circuit to meet the different application requirements.
Keywords/Search Tags:RSA/SM2, Montgomery modular multiplication, Verilog HDL, FPGA
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