Research On Low Power Routing Algorithm For Wired/wireless Hybrid NoC

As the integrated circuit develop, the cores on chip increase rapidly. The high level of integration makes the network-on-chip (NoC) reach some limitations. The traditional NoC is used to connect each routing node with metal link. On one hand, a large number of IP cores lead to the increase of wiring complexity, on the other hand,they also lead to the delay of network transmission and more power consumption. The successful development of on-chip antenna makes the on-chip routing nodes can communicate via wireless links. Because the wireless communication has high bandwidth, low latency, low power and other characteristics, it becomes the potential solution of traditional NoC.The power consumption has been a kind of limitation that cannot be ignored in the design of the NoC. Especially as the level of network integration raises, the power consumption of the chip will be further increased. Then the NoCs will suffer not only the decrease of chip performance, but also the reduction of service life.The main purpose of this thesis proposed a low power routing algorithm for wired/wireless hybrid topology structure. Therefore, this thesis organically combined the 3D-Mesh network and the wireless link, and designed a kind of 3D hybrid topology. And wireless multi hop wireless communication between nodes was realized. Reducing the distance between the nodes, then the power consumption generated on the link could be reduced. In order to further reduce the power consumption, A kind of control method of dark silicon was adopted in this thesis.Making full use of the characteristics of the proposed topology, we designed a set of effective rules. To ensure that it would not have too much impact on the chip performance after shutting down the routing node. This thesis also presented an algorithm of shortest path to reduce communication delay and power consumption,taking advantages of the wireless link's characteristic which can shorten the transmission distance.In order to verify the performance of the proposed topology and routing algorithm, according to the topology structure, a special simulation platform is realized according to the topology structure proposed in this thesis. The performance of the network is tested under different data injection methods. The experiment results showed that the topology and routing algorithm proposed in this paper has similar delay and network throughput, but it greatly reduces the power consumption,compared with the 3D-Mesh structure with the X-Y-Z routing algorithm. It achieves the goal of reducing the power consumption in the condition of not reducing the performance of the chip.