Design Of Zero-Crossing-Detection-Dased Self-Timed Incremental ?-? ADC

In the field of sensor and instrumentation mearsurement,incremental sigma-delta ADC is widely used for high accuracy low frequency signal measurement.With the development of electronic technology,low power gradually becomes the theme for IC design.Low process scale and low supply voltage is required for low power design,but with the scaling down of process,it is challenging to design high gain operational amplifier.Applied in sensor systems,incremental sigma-delta ADC processes huge amount of signals.In some special applications,signals are burst and always accompany with long silent period.The system only cares about signals exceeding threshold range.But massive data sampling and quantification increases the pressure for the system,and the most of power consumption is wasted.To cope with the technique problems above,a zero-crossing-detection-based self-timed incremental sigma-delta ADC is proposed in this thesis,to apply in event-driven high accuracy,low power sparse signal A/D conversion systems.The classical Boser-Wooly second-order incremental sigma-delta ADC structure is adopted.Based on inverter-based zero-crossing-detection technique,opa is replaced by the combination of inverter-based comparator,state-machine-based logic controller,gated current sources to realize charge transfer operation.Charge transfer is divided into three sub-phases: Preset phase,Coarse phase charge transfer,Fine phase charge transfer.ADC adopts differential structure,thus,common-mode feedback technique is utilized to the gated current sources to dynamically control the common-mode for the outputs of integrators.Self-timed technique is realized by “hand-shaking” protocol in mixed-signal processing.Analog integrator works with digital state machine,alternatively switch the operation mode.Based on the output of zero-crossing-detector,logic controller monitors the gated current sources to realize charge transfer.Based on the three sub-phases of charge transfer,the state machine generates clock by itself,so external clock circuit is no more necessary for the ADC.Self-timed incremental sigma-delta ADC is designed and realized with 0.11?m CMOS process.The thesis gives the simulation and cerification results of self-timed sequences,ADC performance and event-driven system.Simulation shows that selftimed circuit works well to provide the clock for ADC.The supply voltage is 1.5 V,conversion rate is 2 kHz,consumes 60 ?W power consumption to achieves 12.8 bits ENOB,the FoM is 4.2 p J/step.Even-driven system reveals that the proposed ADC is suitable for even-driven applications,lower the event ratio,lower the system power consumption.When the event ratio is lower than 10%,the average power consumption is around the level of static power consumption.