Research On Structure Design Of High I_on And Low I_off TFET Based On Electric Field Concentration

With the size of the MOSFET device shrinking,for one thing it brings increase integration of the chip,for another to promote the emergence of the short channel effect,that results in the leakage current increases when device turn off.As a result,the static power consumption becomes more and more prominent as the gate length of the device decreases.In order to solve the problem of chip power consumption,On the one hand,the researchers will consider reducing power consumption in the process of designing the circuit,on the other hand,they explore the way to suppress leakage current at the device level.At present,the researchers not only change the initial structure of the MOSFET,but also to start a new device structure research,especially based on the new working mechanism of the device.The TFET in this paper is a new type of device based on quantum tunneling.Silicon-based TFETs have some advantages which include compatible with conventional MOS processes,very low off-state leakage current,subthreshold swing of less than 60mV/ dec.And also has the disadvantage of low open-state current.In this paper,a vertical TFET with high open current and low off state current is designed by using low-K dielectric and gate-field technique.The contents of this paper are as follows:Firstly,for the traditional silicon-based TFET open-state current is too low,It is proposed to embed a low-K medium and change the electric field distribution in the TFET structure so that the electric field is concentrated in the tunneling junction,thus increasing the tunneling probability and the open-state current,at the same time,that improves subthreshold swing characteristics.Secondly,the medium that causes the concentration of the tunneling junction is studied,including the medium with different dielectric constants,and the position of the medium in the intrinsic region.The conclusion is that the medium with the smaller dielectric constant and close to tunnel junction can get the optimal electrical characteristics.Simulation found that the optimal electrical performance can be gained when the intrinsic region is fully replaced by vacuum.Again,in view of the fact that the medium embedded in the intrinsic region can increase the tunneling electric field,another method of increasing the tunneling field is introduced,namely the gate field plate technique.Simulation of the various electrical characteristics of the device under different length of the gate field can obtain the optimal case of the length of the gate field.At the same time,combined with EFC medium,7.22?A / ?m open current,69.55 mV / dec average subthreshold swing,close to 10-18 A / ?m off-state leakage current can be gained,the data from the SOI-based EFC-TFET.Finally,consider an EFC-TFET based on a common silicon substrate.The application of a common silicon substrate can significantly reduce the cost of the chip,but at the same time there is a risk of increasing the leakage current of the device,by designing an additional layer to suppress part of the substrate leakage current,10-15 A / ?m order of magnitude off leakage current can be gained,While the open state characteristics are determined by the EFC structure.