Research On ESD Protection Device Based On 0.6?m CMOS Process

Electrostatic Discharge(ESD),which is closely related to reliability of semiconductor,is a common phenomenon in daily life.In Integrated Circuit(IC)industry,ESD failure holds a high percentage in the overall failure models,resulting in substantial economic losses.With scale down of critical dimension and ongoing innovation of semiconductor manufacturing,ESD related problems will become more severe.Therefore,research on ESD protection is of great significance in improving reliability of semiconductor.Firstly,this article expounds the ESD protection involved in the design of relevant theoretical basis,including model,design concept in the process of design,common ESD protection module,etc.Model including the physical models and test models.Physical models are mainly HBM(Human Body Model)?MM(Machine Model)?CDM(Charged Device Model)three basic models.Test models mainly includes the corresponding test models of three kinds of physical models,and the TLP test model and IEC test model.In the beginning,this thesis gives an introduction to the basic theories of ESD protection,elaborates on such three ESD physical models as Human Body Model(HBM),Machine Model(MM)and Charged Device Model(CDM)and also explains the testing methods of TLP and electron gun.Common protection devices in CMOS process are introduced,among which are analysis of diode I-V curve,formula deduction of Avalanche breakdown voltage,specific applied examples of resistance as ESD protection,pros and cons of MOSFET in two different conduction models as well as methods and principles for SCR to reduce trigger voltage and increase holding voltage.This thesis then analyzes tape-out and testing of these common protection devices based on 0.6?m CMOS process and concludes their ESD performances in this process.The main focus is on SCR protection device.Through upgrading the device and adjusting the size,triggered voltage is kept being reduced while holding voltage,being increased.A new type of GCSCR device with low triggered voltage has been designed.When ESD pulse occurs,NMOS is turned on via parasitic RC network.Triggered NMOS substrate current flows through substrate resistance.Then,NPN is turned on.After observing the electrostatic potential distribution and current density distribution by simulation this thesis verifies the working principles of GCSCR.ESD performance is also excellent after tape-out.In the end,this thesis introduces TVS together with its arrays,which is applied in board-level circuit ESD protection.Then,TVS applying circumstances and its features are explained.Furthermore,based on requirement index,three ESD protection devices are designed to be used in a low voltage circuit of 1.8 V.All three devices are based on the condition that external trigger circuit injects current,thus the emitter junction of parasitic BJT is forward biased and then SCR is turned on.The experiment result shows that,when stacked diode or number and breadth of NMOS are altered,SCR device with different trigger voltages can be designed.This SCR device is quite flexible regards to its design.