Fault Tolerant Design Of QCA Adder And Flip-flop

Integrated circuit technology has always been developing rapidly according to Moore's law. With the continual downscaling of complementary metal oxide semiconductor (CMOS) technology, issues such as extremely high power consumption,heat dissipation, and unreliability can easily occur, forcing scientists to investigate new technologies. Quantum-dot cellular automata, proposed in 1900s, are one such notable potential candidate technology to replace CMOS,offering a novel method encode,process, and transfer binary information. At present, the QCA circuit has been widely studied, such as memory, flip-flop, adder, multiplier has been achieved, and FPGA system construct by QCA is also developing. In addition, stability and fault tolerance of QCA circuit also in researching.The physical realization of QCA circuit depends on the reliability and fault tolerance of the circuit. This thesis dedicates to QCA reliability analysis and fault tolerance design.In the design of combinational logic circuits,we design a new fault-tolerant QCA majority gate based on 3×5 tile. The majority gate guarantees good fault tolerance under single cell and double cell missing defects compared with several previous structures.Besides,a series of new fault-tolerant adders and dividers are implemented based on the fault-tolerant majority gates. To evaluate the performance of the proposed adders,a thorough comparison versus previous adders is carried out. In the design of sequential circuit logic circuits, an improved dual-edge triggered structure and JK flip-flop are proposed in this paper. It can be found that the reliability of the improved dual-edge triggered structure is higher than that of previous designs through the probabilistic transfer matrix and the defect analysis. Furthermore, compared to the previous designs of JK flip-flop,the improved dual-edge triggered JK flip-flop based on the vertically-stacked block has less cell number and smaller area. The simulation results with QCADesigner show that all the circuits have correct logic functions.