Research And Implementation Of Polar Encoding And Decoding Algorithm

Mobile communication system has experienced the great development from the first to the fourth generation.And the fifth commucatication system is studying and experimenting.Mobile Internet and Internet of things will motivate the development of 5G in 2020 and the further.The technical requirements of continuous broad area coverage,high capacity,low power consumption,wide connection and Ultra-Reliable Low latency Communications(uRLLC)will be achieved in the fifth communication system which will bring revolutionary changes to industry.As a key point of communication system,channel coding provides high reliability.Polar code as a new coding technology is by far the first code that can be proved to achieve Shannon capacity.In November 17,2016,polar code scheme was proposed in the 3GPP RAN1 87 meeting and eventually it became the control channel coding scheme of Enhance Mobile Broadband(eMBB)scenario.This thesis studies the encoding and decoding algorithms of polar code.And the choosing algorithms of encoding and decoding are implemented on hardware platform FPGA.Firstly,the basic theory of channel polarization is introduced combined with the phenomenon of polarization which helps to reveal the essence of channel polarization.Three solutions are provided to solve the estimation problems of polarized channels and comparisons are made to conclude the advantages and disadvantages of these solutions.Finally,the Gaussian approximation is adopted as the method of estimation in this thesis.Then,researches and simulations are focused on the encoding and decoding algorithms.Systematic and non-systematic polar encoding algorithms are compared and analyzed while BP,SC,SCL,CA-SCL decoding algorithms are also analyzed.Non-systematic and CA-SCL algorithms are chosen as the implementation algorithms on FPGA platform.This thesis pays much attention on the design and implementation of the choosing encoding and decoding algorithm based on the analysis of algorithms.Modules are divided and structures are optimized in the process of hardware designing.And the interface lists of core module are provided.The designed circuits are verified from the perspective of functional simulations.And protyping verifications are finished in Altera DE5(chip model: 5SGXEA7N2F45C2).The test and demonstration system is established based on PCIE interface to further prove the correctness and stability of the circuits.Polar encoder occupies less than 1% of the overall resources and maximum working frequency is 610 Mhz.The maximum throughput is 750 Mbps.Polar decoder accounts for about 7% of the overall resources and maximum working frequency is 338 Mhz.The maximum throughput is 229.02 Mbps.