Design Of The Data Transmitter For 6.25Gbps High-Speed Serial Multi-Protocol Interface

Serial communication has become a mainstream trend because of its low power consumption, high-speed and anti-interference ability characteristics. It is widely used in embedded systems, bus systems, networks, etc, and has corresponding industry standards to support, such as Rapid/IO, PCIE, XAUI. These protols have similar serial transmission data rate, but have different electric characteristics in physical level to some extent. Based on universal interface requirement, this paper designed a transmitter circuit for Rapid/IO, PCIE, XAUI these three protocols.The paper combined with mentioned protocols' specification requirements and the signal integrity faced by high-speed serial communication, divided the whole transmitter circuit into three modules including a clock generation(clk gen) module, 10:1 parallel to serial convertion(p2s) module and a driver with pre-emphasis. Especially the driver module adopted SST(Source-Series-Terminated) architecture with 3-tap pre-emphasis used as a driver to a transmit circuit. This topology has realized the terminal impedance, output amplitude and pre-emphasis independently adjustable at the same time. Finally, the paper analyzed the layout techniques and the design rules in detail and completed the whole layout design of the transmitter circuit based on 65 nm CMOS process.The paper used the Calibre tools in Cadence to have an R+C+CC layout parasitic parameter extraction and carried out a simulation on the layout level. The post simulation results display the circuit can achieve 6.25 Gbps data transmission, 520mV-1280 mV differential output voltage range and 2.48 ps of the maximum jitter from eye diagram under typical condition. Besides, the 3-tap pre emphasis can achieve the maximum compensations respectively are +5.24 d B for pre_shoot and-8.05 dB for de_emphasis. The simulation results indicate that the design of the transmitter circuit has a normal function, good performance, stable working state, and satisfy the requirement of the multi-protocol design electrical level indicators. The whole layout area is approximate to 387.27 um X 117.37 um.