Optimization And Physical Design Of DSP-DX’s Fetch And Dispatch Unit

DSP-DX CPU is a new generation DSP Core which can perform both fixed point and floating point arithmetic, and it is based on the eight-way very long instruction word architecture. The DSP with traditional VLIW architecture has large size of instruction codes and low store-access efficiency. To solve these problems, we introduced16/32bit mixed instruction word technique and nonaligned dispatching technique. The logic structures of these techniques were implemented in instruction-fetch station and instruction-dispatch station, thus both the complication and delay of the instruction fetch and dispatch unit increased. To achieve the design aims, we need to optimize the logic architecture and timing of the instruction fetch and dispatch unit with40nm process under the worst condition.Based on the design requirements of DSP-DX CPU, the main works in the paper include:1. To suppress the code size and improve the execution efficiency, we introduced nonaligned dispatching technique and16/32bit mixed instruction word technique for the instruction fetch and dispatch unit, then we designed and verified the unit’s structure, especially the producing circuits of the parallel bit ID, branch ID and control bits of the unit. Finally, the parallelity of instruction execution improved and the unit functioned.2. We completed the timing optimization of key modules by the method of micro-architecture optimization. We synthesized and optimized the instruction fetch and dispatch unit with DC compiler, found out the key path, determined the optimization strategy for each module, and adjusted the logic structures in the key path. The results indicated that we had successfully eliminated the key path delay, and the unit achieved the design goal.3. We finished the physics design of the instruction fetch and dispatch unit by semicustom design method. The design passed the DRC and LVS check, and had good timing.