Research And Implementation Of Basic Functions Based On Digit Recurrence Algorithm

Basic function, as common operation in high performance computing, image processing and digital signal processing, is a combination of constant, root of variable n,index, logarithmic, trigonometric, and inverse trigonometric functions. These basic functions are variety, complex and of big delay and in high precision calculation, these problems are more obvious. Since the 1970 s, a lot of research of hardware design for floatingpoint basic function has been carried out because the calculation speed of hardware is faster than software. However, hardware design of basic functions still stay in theoretical research stage and was not used widely in practical application for the large consume and low latency of floating-point functions.Digit-recurrence algorithm, such as SRT algorithm and CORDIC algorithm, is a main method to realize the basic functions because of the simple operation and the small consume. However, the rate of convergence is slow and the latency of digit-recurrence algorithm is large. After further study of SRT algorithm and CORDIC algorithm, this paper proposes a unified calculation model based on digit-recurrence algorithm to implement basic functions efficiently. Besides, improvements are done to the traditional algorithm through forecasting mechanism and parallel iteration, then a unified parallel acceleration model for basic functions is proposed based on the improved digit-recurrence algorithm.The following research is carried out in this paper:1?Low-latency and parallel SRT algorithm based on remainder and quotient prediction is presented in detail which can be applied to the division and square root calculation.The data relation between iterations is eliminated through remainder predicting mechanism and parallel iteration, so that the parallelism of the improved SRT algorithm is good and the computing cycles can be reduced. The SRT-16 algorithm improved in this paper which can achieve high speed is implemented by overlapping two SRT-4 iterations in one cycle and the hardware cost is small, so it has great practicability.2?Low-latency and parallel CORDIC algorithm based on direction prediction is also presented in this paper which can be used to realize transcendental functions. The algorithm, which can be finished efficiently through direction predicting?parallel iteration and linear approximation iteration, is used in butterfly operation in this paper to realize the FFT accelerator.Results of experiments show that based on improved SRT algorithm, the area of division and square root unit after layout is only 37795um2, the power is only 81.19 m W and the latency of critical path is only 656 ns. And based on improved CORDIC algorithm,the FFT accelerator with one butterfly unit only consumes 8211 REG and 35547 LUT to finish the double-precision floating-point calculation and achieves the frequency of127 MHz. Both of the two improved algorithms have great expansibility and practical significance.