Design And Verification Of M-DSP Scalar Memory Access Controller

The rapid growth of application requirements put forward higher demand of the performance of the DSP, thus prompt DSP to apply new architecture constantly and develop towards multi-core structure. With the continuous improvement of semiconductor process and IC design technology, the integration degree of integrated circuit chip has always been progressed on the basis of Moore's law. However, the "Memory Wall" problem resulted by the gap between CPU and memory has become the bottleneck to further enhance the performance of microprocessors, particularly in multi-core structure. How to mitigate the "Memory Wall" problem in multi-core DSP, and efficiently maintain data consistency is a major challenge for designers. M-DSP is a high-performance 32 bit multi-core DSP developed by our research group independently, which applies VLIW structure which support parallel execution of vector and scalar in each DSP kernel, it can issue 11 instructions concurrently in a clock cycle, has a higher instruction level, data level parallelism and peak performance.Based on the M-DSP multi-core structure and functional design requirements, this paper designs the scalar data memory access controller of its DSP kernel, implements the scalar access pipeline including L1 DCache, and meanwhile implements the consistency maintenance mechanism of programmable scalar data Cache at a relatively low hardware overhead. The main work and innovations of this paper reflected in following several aspects:Firstly, design a set of instructions and coding which support four sizes of accessing including half word(16 bits), single word(32 bits), double words(64 bits), four words(128 bits) and multiple addressing ways.Secondly, design the scalar data access pipeline which can access shared data space and private/shared configuration space respectively, implement the functions of the scalar access pipeline including decoding, address calculation, memory accessing, data selection and submission, etc.Thirdly, support Cacheable or Un-cacheable access which can be configured, design and implement L1 DCache with 64 KB capacity.Fourthly, support programmable operation of L1 DCache write back and cancellation, design the registers to control write back and cancellation operation of L1 DCache, implement the write back and cancellation operation through full pipeline.Fifthly, support the scalar access instructions to access private configuration space in M-DSP cores and shared configuration space including synchronous unit, design and implement the Config pipeline and shared synchronization unit, provide hardware support with low-overhead for the maintenance method of programmable multi-core data consistency.Sixthly, realize multi-level verification for the design comprehensively. Build module-level verification platform with System Verilog, and implement the verification driven by coverage through assertions and constrained random excitation, and create a peripheral storage model for single core system-level verification platform. This design is verified with assembly language in system level. The results show that the functions designed are correct, and the code coverage is approximately100%.Finally, under the constraints of 1.5GHz clock speed, the design is synthesized, optimized and analyzed based on 40 nm technology. The timing results meet the design requirements.