| With the popularity of the internet and diversity of network applications, the data stream of network presents the explosive exponential growth, together with the rapid development of the network routing devices. Therefore, the multi-core network processor based on heterogeneous structures becomes the major candidate for core of routing devices.In order to improve the performance of the packet processing unit of the network processor. This paper concentrates on the characteristics of multi-core architecture, the process of multi-thread packet processing unit, the access of packet processing unit to the external memory and some other issues, and then proposes a method to resolve the "memory wall" problem between the processor and memory performance, using asynchronous memory access mechanism. First of all, this paper brings forward asynchronous memory access mechanism, which is based on the external access flow. And then advances the definition and design of important modules in access mechanism: the definition of instruction and 60-bit command, the concept of signal events; The execution of asynchronous access instruction in the packet processing unit in 5-stage pipeline, and the design of the command FIFO; The design of the command bus arbitration policy; the odd and even periodic solution for data transmission process; Lastly, the paper summarizes the execution steps of asynchronous memory access.With the definition of the formation of instructions and commands, the circuit implement of how the commands of access mechanism come into being, the command arbiter and the data bus is given, described by Verilog hardware description language, and functional simulation verification has been done on RTL code, whose result prove the validity of the design of access mechanism. In the end, packet processing unit has been synthesized by using Design Compiler using library of SMIC 0.13μm and the area is 0.335 mm~2, the top frequency is 167MHz. |
