Design And Implement Of BP And Vector Reduction Component In 32bit M-DSP With High Performance

With the rapid development of science technology, the amount of digital signal data increase explosively. It has brought a large challenge to performance of DSP that how to process so big data.M-DSP is a 32-bit high performance DSP processor, which is independently researched and developed by National University of Defense Technology. It supports VLIW technology, SIMD technology and works at the frequency of 1.0GHz. This thesis, under the background of developing and designing M-DSP chip, has carried out the design of the Bit-Processing(BP) unit and Vector-Reduction unit of the high performance DSP. The main contents are as follows:1. BP unit is designed, implemented with some optimized scheme in its timing, area and power, so the synthesis result satisfy the requirement of M-DSP. According to the design demand of M-DSP arithmetic unit, BP component can execute three kinds of instructions: shift instruction, bit processing instruction and pack & unpack instruction. Both shift instruction and bit processing instruction can support the format of SIMD16 bits. Through the research on the last generation of X-DSP, we find that the structure has the defect that the multiplex ratio of its hardware is too low, which will exert a direct influence on the component's area and power consumption. Based on the optimization of BP component's area, this thesis has combined shift instruction unit and bit processing instruction unit in the aspect of structure. Under the premise of assuring the function unchanged, it has saved one level shifter and improved hardware's multiplex ratio; in the aspect of optimizing power consumption, this thesis has further optimized the power dissipation of BP unit with operand isolation method. According to the synthesis result: compared with X-DSP's BP component, this BP component has been optimized 10.1% of area, reduced 10.4% of dynamic power consumption and 11.4% of static power consumption.2. Vector reduction unit is designed, implemented with some optimized scheme in its timing, area and power, so the synthesis result satisfy the requirement of M-DSP. In the aspect of VPU, it has designed and implemented vector reduction component, which can conduct 8 reduction instruction operations on 16 VPEs, including 4 explicit and 4 implicit reduction mode instructions. Each mode can realize 4 instructions, namely, 2, 4, 8 and 16 reductions. Based on the vector reduction component of Matrix-DSP, this thesis has adopted pipeline optimization method to optimize its timing, and also under VPE's layout, optimizing the length of global signal wire to shorten its critical path; in the aspect of power consumption, it has taken advantage of clock gating to reduce the dynamic power consumption; according to the synthesis result, compared with Matrix-DSP's reduction component, this vector reduction has been reduced 15.4% of proportion, reduced 8.8% of dynamic power consumption and 6% of static power consumption.3. Verify BP component and vector reduction component respectively. 1. Check the rule and grammar of RTL code with Qusetformal. 2. Write Gold model to provide reference for the function of module level and single-core system level's verification. 3. In module level verification we use testbench to check the funtion of BP unit and vector reduction and assembly language in single-core system level verification. 4. Check the controllability of global signal, the function of assembly instruction and coverage of RTL code. 5. Use ATEC and formality to for formalization verifying. The result shows that function of these two components are all correct.