The Channel Estimation In 802.11ax And Its FPGA Implementation

With the ever- increasing demand for high-rate and multimedia data services, people on the requirements of high speed Internet connection have become more and more stringent: not only need to achieve high rate under the limited bandwidth, but also need the large capacity data transmission. Therefore, the future wireless mobile communication systems increasingly need to raise the bandwidth efficiency and channel capacity, this demand greatly contributed to the rapid evolution of the 802.11 wireless LAN protocol, the next generation of 802.11 ax protocol enables multiple users access up to 10 Gbps transfer rate. Since the MIMO-OFDM systems' combination of diversity, coherent demodulation and space-time decoding needs to know the exact channel state information of CSI(C hannel State Information), and the channel estimation accuracy determines the performance of coherent demodulation system,therefore the channel estimation is one of the key technologies in MIMO-OFDM system.This article comes from the 10 g Wi-Fi project which our laboratory in cooperation with a company, the paper focuses on the training sequence based on the channel estimation algorithm research. We are based on LS channel estimation algorithm,In view of the 802.11 ax agreement of the special protocol frame structure,we proposed the use of two training sequences averaging method as channel estimation algorithm for 802.11 ax receiver. Combined 802.11 ax protocol frame structure and characteristics of indoor radio channel, we build a simulation platform system, through a single training sequence as well as two training sequences do simulation contrast averaging channel estimation MSE,the performance of the algorithm to get the appropriate increase computational overhead at the same time greatly improve the channel estimation performance, and it is satisfied well with the 802.11 ax receiver channel estimation performance requirements. In addition,on the basis of the floating-point emulation, and through a large number of simulation, to evaluate the fixed-point algorithm can be realized, and ultimately determine the optimal fixed-point algorithm of the project. Finally, according to the fixed point scheme, the paper achieve channel estimation's key sub-modules of FPGA hardware implementation,in the specific implementation process, This article uses resource reuse, assembly line, parallel design techniques to optimize the hardware scheme,I write the Verilog code,and use ModelSim simulation software for functional simulation, and to compare the simulation results and the Matlab simulation results of the analysis by calculating the two results of the size of the error, it proves the optimal algorithm proposed in this paper have been in hardware design implemented correctly.