Receiver’s Algorithm Design And Fixed-point Simulation In 802.11ax

A huge development of wireless LAN(WLAN) has been witnessed during the last 20 years due to the popularity of IEEE 802.11 devices. On the other hand, challenges in the development of communication technologies emerged mainly in the following three aspects: the exponential growth of data flows, the much higher requirements and expectations from users as well as the tremendous density of WLANs and wireless devices. To solve these problems, TGax working group intends to make a new amendment for the Wi Fi standard(IEEE 802.11ax) before 2019. In order to develop an IEEE 802.11 ax based 10 G Wi Fi protocol so as to provide some convenience in the process of the formulation of the new Wi Fi standard, we set up an IEEE 802.11 ax based physical layer’s simulation platform incorporating both the transmitter and the receiver. In this paper, the receiver algorithms of the physical layer are investigated and some design works and simulations are also conducted in a fixed-point framework, which can provide a strong support for the FPGA realization of the physical laye r both in algorithms and in data.The simulation platform is based on the latest proposals of IEEE 802.11 ax and constructed by using Matlab. In this framework, we investigate the receiver algorithms which are simple to implement in the physical layer, inc luding the preamble-based timing and synchronous algorithm, the frequency offset estimation and phase correction algorithm, the training-based phase tracking algorithm, the channel estimation algorithm in OFDM systems and the MIMO detection algorithm. We a lso conduct some simulations on the performance of the above five algorithms and test the entire float-point simulation system in order to make sure that various metrics of the physical layer(e.g. packet error rate) can meet the requirements under differe nt circumstances. In the basis of the float-point algorithms, we then propose a fixed-point realization scheme for FPGA. Specifically, we set up a fixed-point simulation platform in the Matlab environment and get their performance through simulations, whic h can be further improved by comparing them with the float-point ones. In this paper, we mainly focus on the building process of the AP/STA transceiver system in the 20 MHz mode. The transmitter module consists of the submodules of padding, scrambler, FEC(BCC or LDPC) encoders, stream parser, interleaver, constellation mapper, tone mapper, CSD, IDFT, guard interval(GI) insertion, windowing etc. And the receiver module includes the submodules of AGC, synchronization, FFT, phase tracking, channel estimation, MIMO detection, LLR as well as the submodules that do not need fixed-point redesign, such as deinterleaver, stream parser, decode, descrame ect.Finally, we yield some simulation results over the entire fixed-point simulation platform and demonstrate the performance differences between the fixed-point modules and their corresponding float-point modules. We also show the results of the packet error rate of the entire system when the MCS level ranges from 0 to 9.