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Research Of Defect Inspection Technology For 3D Integration Based On SOM Neural Network

Posted on:2017-10-16Degree:MasterType:Thesis
Country:ChinaCandidate:P F ChenFull Text:PDF
GTID:2348330509459880Subject:Mechanical and electrical engineering
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Three-dimensional integration(3D Integration) has being a crucial research subject and is wining broad prospects, as traditional integration circuits have encountered obstacles in aspects like material, interconnect delay, power consumption and so on. Microbumps and through-silicon-vias(TSVs) are the core of 3D Integration interconnection structures. Defects in microbumps and TSVs will degrade property and reliability of 3D Integration devices, so it's of great significance to develop relative inspection techniques. In this thesis, high resolution X-ray photography and SOM neural network are combined to detect bump-missing defects and void defects of TSVs in 3D Integration. The main contents are as follows:(1) An inspection method for missing-bump defects in 3D Integration is studied. The planar transmission X-ray images of the samples are captured and the microbump areas are segmented with the combination of Canny operator and morphological operations. Feature vectors including the maximum gray value, the minimum gray value, the average gray value, and the standard deviation are extracted for representation of microbumps. A SOM network with 11×11 neurons in the output layer is constructed and trained with randomly selected feature vectors. The trained network can distinguish defective bumps from normal bumps correctly.(2) An inspection method for void defects of TSVs in single layer chips is studied. Feature vectors consisting of 7 features from the gray value domain, the texture and the frequency domain are extracted. A SOM network with 8×8 neurons in the output layer is constructed, trained, and used to distinguish defective TSVs from normal TSVs correctly. Void areas in TSVs are located with OTSU algorithm and are confirmed by grinded cross-sections.(3) An inspection method for voids of TSVs in stacked chips is studied. Three steps are set to segment and repair the TSV areas in X-ray images of stacked chips. The same 7 features are extracted and the SOM network with the same scale is trained and then adopted for recognition of TSVs. The OTSU algorithm is used to locate the void areas and the stacked chips are grinded so that the void locations are confirmed.Above all, a feasible approach for high efficient and non-destructive inspection of bump-missing defects and voids of TSVs in 3D Integration is raised in this thesis.
Keywords/Search Tags:3D integration, Microbump-missing defects, TSV void, SOM neural network
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