Research On Tracking Technology Of High Sensitivity Bei Dou Receiver

BeiDou system is researched and developed by our country, and it has become the third global navigation system after the Global Positioning System of USA and Globle Navigation Satellite System of Russia. As BeiDou navigation network develops, the BeiDou industrial chain contributes a critical effect to the national economic development and national defense construction strategically. Tracking loop directly determines receiver's performance, it's great significant to research high performance and high sensitivity tracking technology.Deeply analysised BeiDou B1 I signal and GPS L1 signal, and the traditional phase-locked tracking loop was built. Loop stability, steady-state response as well as steady state error were estimated in time domain. Loop error source model was established, relationship between error source and loop parameters was simulation analysised. Designed, completed and experienced the traditional PLL loop performance in embedded platform.Further researched the integration time to enhance loop performance. An improved histogram of bit synchronization method was put forward for BeiDou D1 navigation message, this method could quickly achieve bit sync based on histogram and NH code. A coherent integration method that compatible with BeiDou and GPS was put forward, this method could flexible adjust integration time based on bit sync. Completed the coherent integration method based on FPGA and verified the method to enhance tracking the weak signal performance.Although extend integration time could enhance tracking weak signal performance, it can't been extended infinite length and loop tracking precious became bad with poor signal strength. A closed feedback control loop was researched to precise loop information, inhibit loop noise and enhance loop tracking precision. The filter estimation models were built based output discriminator and loop filter. Design, completed and experienced the system model in embedded platform.Finally, the system verification platform was designed based on FPGA and DSP. The FPGA mainly parallel process multiple channels baseband data, and DSP mainly complete navigation algorithm and other complex operation. This framework is mainstream of receiver platform, it provides the test platform for further research about high performance receiver.