Extending Moore's Law

Moore's Law has witnessed more than half a century's development, resulting in continuous increase of integration and improved performance in a chip. However, with the feature dimension of CMOS reaching the nano regime, there are more challenges in device processing techniques, problems such as short channel effect, have worsen the chip performance. According to the forecast of International Technology Roadmap for Semiconductor, the current techniques cannot satisfy the increase demand of high performance, low power dissipation beyond 14 nm node. To keep Moore's Law rolling in the future and balance the contradiction between chip power and performance, device design based on novel materials has been the hot topic among the international semiconductor industry.Based on the above background, this paper employs GeSn alloy, which has high carrier mobility, tunable bandgap etc., through strain engineering and energy band engineering, we investigate GeSn-based high-mobility p-channel MOSFET and low power consumption GeSn pTFET. The main research achievements we have attained are as follows:1) We studied?001?,?011?,?111?-oriented undoped Ge_0.92Sn_0.08 quantum well pMOSFETs with in-situ Si2H6 passivation. MBE method was performed to grow high-quality GeSn film, GeSn/Ge heterostructure formed quantum well. The dependence of GeSn devices performance on orientations was discussed. It's found that?111?-oriented GeSn pMOSFET exhibited the record-high mobility eff = 845cm2/Vs.2) Relaxed Ge_0.97Sn_0.03 pTFET on Si substrate was successfully fabricated. We studied the influence of temperature on the device electrical characteristics, proving that BTBT dominated the tunneling current; for the first time, we applied the 0.14% uniaxial tensile strain on the relaxed Ge_0.97Sn_0.03 device, at VDD =-1V, 10% enhancement in ION was achieved compared to unstrained one.3) We simulated the novel Ge_1-xSn_x/Ge_1-ySn_y double-gate HE-NTFETT. The dependence of SS, ION etc. on the position of heterostructure in the channel was discussed, as LT-H became shorter, BTBT delayed heavily and VONSET got larger. At ON-State, the existence of heterostructure contributed to the reduction of tunneling barrier and enhancement of tunneling current. Ge_0.92Sn_0.08/Ge_0.94Sn_0.06 HE-NTFET with LT-H = 4 nm demonstrated superior performance, the average SS achieved 48 mV/decace, 304% ION improvement was shown compared to GeSn homo device. Adjusting the Sn composition in the heterojunction was beneficial to the enhanced ION and SS.This paper investigated high mobility MOSFET and low power consumption TFET based on GeSn alloy, laying theoretical and experimental foundation of GeSn application in microelectronic field. It helps to extend the Moore's Law in IC and facilitate the development of next generation high performance, low power consumption devices.