Research On Key Technologies Of GeSn Alloys And The Field-Effect Transistor Applications

Scaling of nanoscale MOSFET is quite a challenging work,but it's possible to achieve the goal in accordance with“Moore's law”by adopting high-mobility channel materials or by using novel TFET device whose working mechanism is band-to-band tunneling.GeSn alloys are attracting a great deal of attention due to their tunable band gaps.In addition,GeSn alloys are high-mobility materials,and the possible direct gap properties are also beneficial for boosting the carrier tunneling capability.Hence,GeSn alloys are promising candidates for the future high-performance MOSFET and TFET applications.Considering the great application potential,key technologies of GeSn alloys and the corresponding field-effect transistors are systematically investigated.GeSn electronic band structures are calculated by an empirical pseudopotential method,and the obtained results are helpful to deeply understand the indirect-to-direct gap transition of GeSn alloys.Carrier effective masses are extracted from the developed band information,and the results indicate that high Sn composition is beneficial for the reduction of effective masses in general.Transport and tunneling capabilities of?electrons and holes are also analyzed.For GeSn MOSFET applications,GeSn samples are characterized and their thermal budget limitations are determined.To passivate the interface between GeSn and high-?dielectrics,a Sn-assisted oxynitridation process involving ozone and NH₃ambient treatment is proposed,and a GeSnON interlayer is formed after the passivation process.The formed GeSnON interlayer is useful for reducing the interface trap density of the GeSn MOS stacks.The corresponding MOSFETs with the GeSnON interlayer are also fabricated,and the extracted hole effective mobility achieves more than 4-fold enhancement compared with the Si universal hole mobility.For GeSn TFET applications,GeSn/Ge TFET device characteristics are investigated by device simulations.Both N-and P-channel TFETs are analyzed and the corresponding device structures are optimized.“Hetero-channel?HC?point-tunneling”and“hetero-source?HS?line-tunneling”device structures are proposed to improve the subthreshold characteristics of the simulated GeSn/Ge TFETs.By adopting the optimized HC and HS device structures,driving currents of TFETs are significantly enhanced at the extremely small supply voltages.Strain effects are comprehensively investigated and compared to further boost the GeSn device performance.?001?,?110?,and?111?biaxial strain and[100],[110]uniaxial strain are simulated and analyzed.Band gaps and carrier effective masses of GeSn alloys are affected by the applied biaxial and uniaxial strain.The best biaxial and uniaxial strain configurations are proposed to enhance the carrier transport and tunneling capabilities of GeSn alloys.Guidelines are provided for the design and optimization of high-performance strained GeSn MOSFET and TFET applications.