Design And Simulation On Implementation Of Cyclic Code Parameter Identification

In digital communication systems, channel coding is the guarantee for reliability and security of information transmission, as channel coding technology rapid development and wide application in many fields, the channel coding identification problem have become increasingly prominent. Channel coding identified coding system and parameters according to a small number of the received code word sequence, which is an important step before decoding. Loop coding is simple and with strong ability to rectify error detection, which used in many areas of digital communication, so the recognition problem is also paid much attention. Current research focused on the theoretical analysis of the identifying methods, but a few in the hardware aspects. In addition, the hardware implementation may provide the ideal platform for high-speed and real-time analysis of the identification signal. Therefore, this paper is based on the hardware realization of cyclic code parameter identification to research.For the current cycle recognition algorithm code, most are based on statistical algorithms, that resulting in the required much data and long time, to traverse a long and difficult to achieve and so on, this article is based on hardware to proposed code parameter identification method that a few data,quickly recognition, certain error robustness, easy to realize on FPGA. Based on any of the code is its cyclic code word polynomial times,received code word sequence in accordance with a preset length segmentation, after the verdict division remainder is zero if the threshold meet number of times, and then identify the parameters of cyclic codes. Theoretical analysis and simulation to verify the feasibility and error robustness, the method in the error rate under 0.007, which can effectively identify the code length and cyclic code generator polynomial. Then, to complete this process include segmentation code sequence, the each module design identification of code word by Verilog HDL hardware description. Based on the shortage of this design that can't recognize the same code length, different rate primitive cyclic code, this article use hierarchical categorize ideas in pattern recognition decision tree as the reference, constructing corresponding identification rules, to improve the entire design. Finally, to realize the last improved idea on the FPGA, simulation results of Modelsim SE10.1 software verify the feasibility the cyclic code parameters to identification.