The Development Of Data Allocation And ARM-FPGA Bus Interface Of Small PLC

This research is about a small PLC system based on ARM+FPGA structure. In the PLC, the FPGA part is responsible for the completion of timing, counting, input and output, multi-bit logic operation. The ARM part is responsible for the static and dynamic compilation of PLC instructions, as well as the data configuration of ARM's memory and FPGA's function module. ARM and FPGA complete the execution of PLC instruction as of its cooperation.This project based on the existing research mainly research the method of PLC data configuration, the ARM-FPGA bus interface and protocol, the exception handling mechanism of PLC, and the optimization and improvement of designed PLC system. The main achievements are as follows:(1) The design of PLC data configuration. The data structure static compilation of PLC instructions is designed. the static compilation effectively solve the problem of operating efficiency and storage space of PLC instruction using variable instruct length and sequence storage. And the timer and counter format, and the jump address storage method is designed to solve the ARM initialization configuration of the timer and counter in FPGA, as well as the jump address configuration problem of jump instructions. To basic instruction and application instruction, according to the results of dynamic compilation,they are converted to FPGA format for data, then configure the FPGA through the ARM-FPGA bus. According to the FPGA of each function module's calculation results,configure the soft components and storage area in the ARM dynamically.(2) The design of the ARM-FPGA bus interface and protocol. The requirements of exchange of data according to the design of the dual port RAM and ARM and the characteristics of FPGA, the parallel interface ARM external memory interface is designed based on ARM-FPGA bus. According to the characteristics of dual port ram, and the requirements of data exchange between ARM and FPGA, a kind of ARM-FPGA bus on the basis of the parallel interface ARM's external memory interface is designed. According to the characteristics of each function module of FPGA, and the characteristics of PLC basic instructions and application instructions, the data transmission format between ARM and FPGA is designed, those laid the foundation for the realization of ARM-FPGA communication.(3) The design of PLC API interface, the shell command and the exception handling mechanism. These design improve the function of PLC system. The exception handler can capture the exception when PLC system is running, and then make appropriate treatment to ensure the safety of PLC in operation. For development of PLC easy, API interface forcommunication between external devices and the ARM master is designed. It provides a unified standard for application layer communication protocol of external equipment, such as man-machine interface, PC, handheld programmer. The PLC shell command is designed, the PLC shell can manage and control PLC system, and through the shell command, can view exception information, which is propitious to system debug.(4) The test of data configuration of PLC, ARM-FPGA communication, exception handler, PLC API and shell. Through the test results show that: the PLC system can correctly configure the data in the static and dynamic compilation; ARM-FPGA bus can realize communication of ARM-FPGA orderly and efficiently; The PLC API can meet the needs of communication between PLC and man-machine, interface, PC; The shell command can look up and set PLC status; The exception handler can capture the exception and handle it correctly.