Implementation And Optimization Of Concurrent Access Of S-box For Block Cipher Algorithm

S box substitution unit is a part of the nonlinear computation in cipher algorithms. It's used to confuse the relationship between the fuzzy text and the cipher text. Reconfigurable system is suitable for data-intensive applications due to the combination of flexibility and efficiency. Cipher algorithms need to deal with large amount of data. The combination of cipher algorithms and reconfigurable technology can meet the requirements of performance and security. When applied in the reconfigurable cryptographic processor, using logic circuit to realize S-box has no flexibility to achieve a variety of cryptographic algorithms. Also due to som S-box function constraints in cipher algorithms, such as DES, logic circuit can't realize the substitution function. Look-up table is a better way. However, Look-uo table has brought huge consumption of area resources impacting the entire system performance. Therefore, it is an important task to design a S-box substitution unit structure with hign performance for block cipher.In this thesis, a set of area-aware S-box substitution unit which is suitable for block cipher algorithm is put forward from two aspects. One aspect is circuits, and another aspect is architecture. In circuits aspect, through analysis of the block cipher S-box substitution features, look-up table operation mode, concurrent access can be analized. Then software model for design concurrent access TLU is proposed based on design constraints. Hardware design of full custom memory is complited. The whole area decreased supporting the same concurrent access In architectrure aspect, reconfigurable concurrent access S-box replacement unit is put forward in order to solve large area resources consumption caused by the large data width and large table capacity table. A shared memory lookup table structure based on multi port concurrent access memory is put forward in order to solve large area resources consumption caused by storing multiple copies of the same S-box information to achieve high degree of concurrency which is a huge number. After doing these work, as the results show, area and performance are both optimized.The SRAM circuit was implemented by using SMIC 40nm CMOS technology. Circuit operating frequency was 500MHz. The shared-storage concurrent access TLU was about 26467?m2 consists of four 4-port 256 X 8bits SRAM whose area was about 6002?m2. While applied in the reconfigurable processor with the same concurrent access for kinds of S-boxes, the concurrent access lookup table's area designed by this thesis was about 68.69% smaller. And average area efficiency was 3131.87 bits/mm2/cycle. What's more, the concurrent access lookup table's area efficiency designed by this thesis is 235.28% higher than Cryptor,160.63% higher than RPU,29.23% higher than RCPA, and 108.15% higher than COBRA.