Based On Fpga Sata2.0 Encryption Bridge Controller Design And Research

SATA embedding with data and commands checking unit is a high speed serial bus, which transfers data by point to point transfer mode with 150MB per second (SATA version 1.0) or 300MB/s (SATA version 2.0), and supports hot plug and play. The products of SATA version 2.0 is widely used than that of SATA version 1.0, because it can support some technology features, such as NCQ, port multiplier, interleaving start-up, hot swap and so on.As information technology has been developing quickly in our country and has widely spreaded in industry, commerce and daily life etc, information and data security become more important than ever befor. The encryption technique based on hardware has features of high speed and reliable way of secret key encryption, so it gradually becomes the trend of data encryption. This paper integrates hard disk encryption and SATA version 2.0 interface, and has realized hard disk encrypton bridge with SATA verison 2.0 interface by FPGA, which is very important to research hard disk encryption bridge with high-speed serial interface.The difference between of Parallel ATA protocol and Serial ATA protocol has been introduced in the paper. SATA version 2.0 standard and ATA/ATAPI-6 command set, which include physical layer, link layer, transport layer and application layer, has been studied detaily. The internal block diagram and operational principle of Xilinx company's Virtex-5? GTP is also expatiated in this paper. Paper focus on the system design of SATA version 2.0 encryption bridge IP, analysis of transmission mode of encryption bridge's primitives and frames, a detailed briefing of every module's operational principle, and the main points of the realizaion wich should be noted.Rererring to design flow, the fist stage of SATA2.0 encryption bridge controller IP is system level programming. The job is making specification of hardware's interface and function, including signals'names and related timing. At the second stage, the circuit should be described by Hardware Descript-Language (HDL) according to the specification. Verification guarantees the correctness of the RTL codes. During design, not only area or power, but also validness must be taken into account. For enhancing robust, many principles can be follewed at the beginning of RTL design, besides sufficient verification is supplement. Thus, papers also present the system verification. Encryption bridge controller IP wokes normally on Xilinx Virtex-5? FPGA with good performance and reaches perfomance requirements. The research fruit of SATA2.0 encryption bridge controller design and realize based on this dissertation is referential and it can be applied into other projects.