High-precision System Verilog Model Of Graphics Processing Unit Memory System And Automated Simulation

The memory system is an important part of a graphics processing unit, which provides essential random-access-memory for the computing cores, and affects the performance of the whole chip remarkably. During the design of the memory management module in a graphics processing unit, a function model, for supporting the design and finding error points quickly, is needed to be built synchronously. What is more, the actual DDR controller costs much time to simulate, and a fast-simulating DDR controller model is needed.In this thesis, a high-precision and fast-simulating DDR controller model has been built using System Verilog. It has no timing error at low workload, and the average timing error at high workload is less than 5.8%. The model is 260 times faster to simulate than the actual memory controller, which makes the simulation of the whole memory management module 10 times faster, and decreases the time expense of simulation greatly during the design of the chip.Based on the memory controller, a model of the whole memory system has been built. The model includes 7 streamed reading/writing channels of different data width, along with data width conversion modules to split and merge data between any widths. Also, a parameterized arbitrator with definable priority has been build.According to the memory access pattern of each of the 3 key channel, 3 different caches have been designed to optimize their performance. To optimize the accessing speed of DDR controller, a out-of-order data adjustor has been designed. The model is faster to build than the RTL thanks to the coding language difference, making it very suitable to pre-design an arithmetic prototype before a new idea is used in the RTL, so the chip design may be faster.In this thesis, a highly automated parallelized simulation environment has been built, with convenient shell scripts and two supporting softwares. One software is used to start several parallel simulations automatically, and the other is to automatically compare the simulation result files according to the rules. By using the simulation environment and the two softwares together, 30 or more simulations can be started with just "one click of the mouse", making full use of the workstation's compute power, and the work efficiency can be greatly increased. By applying the environment to the actual chip design, the fragmented human operation of simulation controls, originally scattered in 23 workdays at most, can be concentrated into simple operations within 1 minute. It saves much human labor and allows the whole project to advance faster.