Research On The High Reject-ratio Clipping Unit And Full-system Simulation Platform For Embedded GPU

With the rapid development of embedded devices, especially smart phones, the graph-ics display quality and resolution of embedded devices has become rapidly attractive inrecent years. The fact that CPU is barely able to meet the rendering requirements of graph-ics has made embedded graphics processing unit(GPU) increasingly promising. Thereforethe study of3D GPU applied in embedded devices becomes a hotspot of manufacturers andinstitutes. Though embedded GPU is similar to traditional GPU in function, the numberof programmable shaders in embedded GPU should be limited strictly due to constrains ofarea and power of embedded GPU. Considering this condition, maximal reduction of tri-angle processing that are out of the particular scene can be obtained and the overall perfor-mance can be significantly improved as well. On the other hand, as the scale of componentsintegrated on a chip increases rapidly, the design of embedded GPU is expected to be chal-lenging in the future, giving rise to a prolonged design lifecycle of the micro-architectureof embedded GPU, system software development and software-hardware co-verification.To solve the issues mentioned above, this paper focus on the study of the clippingunit of embedded GPU and the full-system simulation platform, providing a solid basisfrom both theoretical and technical perspectives. Major contributions of this paper can beconcluded into two points.Firstly, a clipping unit with high reject-ratio is proposed in this paper. Clipping, acritical of the graphics pipeline, aims to reject the triangles located outside the scene andhence reduce the computations of rasterization and subsequent units. In this paper, theclipping unit is divided into two stages: pre-clipping stage and clipping stage. In pre-clipping stage, we propose to combines outcode method with the slope judgment method,The evaluation experiments have shown the reject-ratio of pre-clipping stage is increased bymore than10%. In clipping stage, double clipping planes are utilized to clip simultaneously,which remarkably decrease the cycles in clipping stage.Secondly, a full-system simulation platform for embedded GPU is proposed in thispaper. This simulation platform is able to provide a complete software-hardware co-designand co-verification environment with high abstract layer during the early period of the de-sign of embedded GPU and SoC system, which ensures the product feasibility and reducesthe overheads of hardware design followed.