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Design And Realize The IP Core Of 3D Embedded Graphics Processing Unit Based On FPGA

Posted on:2011-06-21Degree:MasterType:Thesis
Country:ChinaCandidate:X Q TanFull Text:PDF
GTID:2178330338976237Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
Graphics processing system is an important component of modern computer system, traditional graphics processing system usually adopts a dedicated graphics processor GPU to alleviate the burden of CPU to process graphics, with the needs of graphical display of electronic products continued to improve, it is necessary for the embedded system to own a dedicated GPU to handle more complex graphics. The development of the traditional graphics processor has a relatively mature, but there are many issues on the research of the high-performance GPU which suit the embedded systems. So researching and designing the embedded GPU makes great sense.Based on an intensive study of computer graphics and related algorithms, the thesis firstly reviews the history of GPUs and its rendering mechanism, then it analyzes the components of graphics system. This thesis adopts OpenGL as its graphics API, selects 21 most commonly used commands from OpenGL, and defines the rendering lists and command word encodings for these selected commands, these rendering lists and command word encodings will be used as the IP core's design specification. The graphics pipeline is divided into geometry and raster, and eventually broken down into eight modules which will be realized with Verilog HDL language on four FPGAs. The thesis analyzes and designs the modules of GPU in detail, it focuses on the implementation of the scale and combination transformation for the geometric transformation module, the handling of two light sources for the illumination module, the excluding, shearing and anti-aliasing of the triangle primitives.The IP core design, build, debug and integrated simulation are completed in Quartus II 6.0. The operating frequency of IP core is 50MHz, and IP core's logic resources occupancy rate of FPGA is about 80%, A total of occupation within the logical elements less than 60000. Finally on the Verification platform the IP core can able to correctly execute all the selected APIs, and can do translation, scaling, lighting calculation, eliminate cut, and rasterization with Three-dimensional objects and so on.
Keywords/Search Tags:Graphics Processing Unit, GPU, graphics pipeline, IP core, Verilog HDL
PDF Full Text Request
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