Design And Implementation Of High Speed Cache Base On STT-MRAM

As feature size continues to decrease, leakage power ratio of the total power being increased year by year. More than half of the area and leakage power are generated due to the high-speed cache memory in the central processor, cache area and static leakage are becoming a bottleneck restricting the development of memory. Now ordinary cache makes from the static random access memory SRAM, although SRAM has high read and write speeds with CPU rivals, but the huge area can not eliminate the leakage power which restricts the development of high-speed cache, and also, it is volatility memory.Common method of reducing the power consumption is cache clock gating(power gating) technology, which by reducing the supply voltage of SRAM, but the gated clock will certainly increase the area at the same time does not eliminate leakage power features. Among the non-volatile memory technology,torque transfer magnetic memory STT-MRAM because of its small size, non-volatile, high reading speed, lower power consumption and leakage compatible CMOS technology is becoming a today's most promising high-speed cache. However, the high write currents are limiting the development of the next generation STT-MRAM.This article do a study of MTJ and STT-MRAM technology and caching technology, and proposed a new structure based on the high-speed cache asymmetric STT-MRAM writing characteristics, mainly as follows:(1) according to the physical characteristics of STT-MRAM, such as: thermal disturbance, the resistance Gaussian distribution, precession flip and thermal disturbance features verliog-A is designed to use STT-MRAM dynamic behavior model and design the STT-MRAM write write circuits.(2) Using STT-MRAM model to simulate the behavior of the asymmetric read, and record the associated delay and the current.(3) According to the STT-MRAM writing characteristic asymmetrical design of the new cache architecture(4) Using SYNNOPSYS Design Compiler to compile Verilog code.(5) According to the new cache structure and model parameters, in NVsim environment simulated power consumption and area.