Key Techniques Of Low Power ECG Singal Processor

With the development of society economy and health consciousness, traditional medical equipment can't meet the growing demand for portability, while the portable wearable medical equipment becomes a new research hotspot, so people who use the real time and hammerless medical equipment come up with higher requirements for power consumption and volume. This paper chooses ECG signal as the studying object, by a series of measures of signal de-noising and feature point extraction, achieving the purpose of ECG data compression. And then decrease the data flow of RF module to achieve the purpose of reducing power dissipation.Article comes up with a complete solution for ECG signal through analyzing the characteristic of it. Algorithms: using the wavelet shrinkage algorithm to wipe out motion artifacts and electromyography, cooperating with biquad IIR filter to wipe out power frequency at the same time, at last, with abandoning wavelet coefficient of 8 floors, baseline wander was removed successfully. It was proven effective to de-noise and protect the feature points properly at the same time. Dynamic modulus maxima pair QRS complex detection algorithm makes that ECG signal was decomposed by using 4 floor stationary wavelet transform to realize feature extraction. R peak detection rate nearly reaching 100% thanks to the error detection and leak detection algorithm, which make sure the reliability of algorithm and low algorithm complexity at the same time.Hardware: Insitute of Microelectronics of Chinese Academy of Sciences proposed Programmable and Re-Configurable hardware architecture was performed as the main hardware platform. Similar and high density operation was dealt with the Re-Configurable processor, while the irregular operation, task scheduling and controlling, and function extension and algorithm upgrading were realized by the means of programmable ARM Cortex M0, which strikes an average between the ultra low power consumption and flexibility. For the sake of reducing power consumption, clock gating, memory data reusing, and multi VDD were adopt. What's more, logic function has been verified and completed back-end design and layout with the SMIC 130 process.