Study On Effect Of Annealing Conditions On The Capacitance Characteristics Of MOS 4H-SiC/SiO2

With advantages of wide energy band, high breakdown electric field and high thermal conductivity, etc, silicon carbide（Si C） is a great third-generation semiconductor material. Si C MOS device which is extremely suitable for working condition and environment of high temperature, high frequency, heavy duty and intense radiation, has great application potential in aeronautics, nuclear energy, and communication, etc. However, poor quality and high density of Si C/Si O₂ interface lead to lower inversion channel mobility, the increase of threshold voltage and low-frequency l/f noise, which significantly limits performance of Si C MOS device. The research on improvement of interface quality, lowering of interface state density of devices is a hot issue, in which annealing process after oxidation is a proven effective approach.The effect of annealing gases（NO, Ar, N₂） for 4H-Si C/Si O₂ Si C MOS structure is researched in this paper. The N-type 4H-Si C MOS capacitance samples annealed by the three gases are measured and analyzed.In C-V test of samples, positive bias of flat band voltage of NO-annealed sample is less than other two samples.In addition, oxide trap density Not, near-interface oxidizing layer density Niot, and interface state density Dit of NO-annealed sample are all obviously lower than other two samples, which shows that NO annealing can effectively reduce interface state, near-interface oxidizing layer density as well as interface state density.I-V test results show that the Fb value of NO-annealed sample which has lower interface state density is higher, which means that sample is less prone to leakage.In voltage stress test, forward bias of flat band voltage of sample is on the rise with accumulation of voltage stress time. Flat band voltage for the samples annealed by NO and Ar is tended to be stable after a certain period of time for voltage applied. Flat band voltage for N₂ annealed sample is sustained increase with accumulation of voltage stress time, which is shown than voltage endurance reliability of N₂-annealed sample is very poor. Under high-temperature tests, CV and GV curves is measured respectively at 25 ℃, 75 ℃ and 150 ℃. Under high temperature conditions, the filling of the charge traps is morepossibilty to happen. The filling of the electron to the trap leads to the positive extension of the C-V curve for Ar and N₂ samples with the increase of temperature,as well as the G-V peak which is away from the Ec about 0.2e V is decreased. However, in the NO sample, the hole traps are introduced. And the competition of the two kinds of effects is caused by the hole and electron filling in the test process, which leads to the trend shake of the C-V curve, and the overall dominant of the hole filling lead to the negative extension of the C-V curve with the temperature increase. While in the NO sample, the G-V peak which is away from the Ec about 0.2e V is decreased, but the peak of the G-V peak（corresponding to the ON1 trap） in the deep level position is rise. Those two phenomena reflect respectively that the former can not be released immediately after the charge filling, and the latter is easy to be released after the charge filling so that it can respond to the small AC signal in the test.In conclusion, better overall effect improvement on interfacial properties of the NO annealed samples is proved. At high temperature, however, the charge filling effect may cause for device threshold voltage instability.