Investigations On Degradation Mechanism Of 1.2kV 4H-SiC JBS Diodes Under High-temperature Reverse-Bias Stress Test

By virtue of the superior electrical and physical properties,the third-generation wide band-gap semiconductor silicon carbide?SiC?has been widely researched and utilized.In compared with traditional silicon?Si?and germanium?Ge?,4H-SiC is considered to be a preferred material for manufacturing high-performance devices because of the higher critical breakdown electric field and higher thermal conductivity.Instead of the Si power devices,4H-SiC devices is used in a system,in which the cooling equipment can be eliminated.The volume and cost of the 4H-SiC devices system can be reduced greatly.As a representative of 4H-SiC power devices,4H-SiC JBS diodes have been commercialized.However,to allow broad applications of 4H-SiC JBS diodes in power electronics system,there are still some issues to be solved,especially the reliability of 4H-SiC JBS diodes exposed in the application process.Especially,the stability and related degradation mechanisms induced by HTRB?High-Temperature Reverse Bias?have not yet been clear.In this paper,the electrical parameters shift,the corresponding degradation mechanisms and structure optimization for 1.2kV 4H-SiC JBS diodes terminated non-equidistance field limiting rings?FLRs?submitted to HTRB have been studied in detail.The main research methods and contents are as follows:Firstly,the shift of the electrical parameter of 4H-SiC JBS diodes under HTRB test at room temperature and elevated temperature is studied.A stress of 400V,700V or 1000V is applied to the 4H-SiC JBS diode at room temperature for about 3.3h,respectively.The electrical characterizations were performed by Agilent B1505A Power Device analyzer/Curve Tracer after every 20 minutes interval,including the reverse and forward I-V characteristics.The results show that the forward characteristic parameter of the device are stable and do not degrade with bias stress.However,the breakdown voltage(V_BR)of4H-SiC JBS diode increases with the stress time and the degree of reverse-bias stress and reaches the saturation(V_BRSAT)at room temperature.At room temperature,the increments of breakdown voltage of 4H-SiC JBS diode at 400V?700V and 1000V are 50V?60V and120V,respectively.A bias stress of 1000V is applied to the 4H-SiC JBS at 60?,125?and 175?,respectively.The experimental results show the forward characteristic parameter is still not degrade with bias stress.But,the degradation trend of V_BR at elevated temperature is similar to the results at room temperature.However,the saturation breakdown voltage V_BRSAT of 4H-SiC JBS diodes decreases with increasing temperature at elevated temperature.The increments of breakdown voltage of 4H-SiC JBS diode at 60?,120?and 175?are 230V,180V and 150V,respectively.Secondly,the degradation mechanism of 4H-SiC JBS diodes induced by reverse-bias stress is investigated at room temperature and elevated temperature:It is believed that the holes will be injected into the 4H-SiC/SiO₂ interface and the oxide layer induced by the reverse-bias stress for the 4H-SiC JBS diode terminated non-equidistance FLRs by the Sentaurus TCAD software simulation and experimental results.The trapping holes at the4H-SiC/SiO₂ interface and the oxide layer lead to the reduction of the total negative effective interface charge.The reduced negative effective interface charges due to the hole injection will slow down the surface depletion of 4H-SiC n-type drift layer and make the more sparse potential distribution on the outer part of the p+FLRs,resulting in relieving the electric field crowding effect,and increasing the breakdown voltage.The degradation mechanism enhances when the reverse-bias increases.During the post-stress period,the trapped holes induced by the reverse-bias stress are gradually recovering toward the pre-stress states,so the breakdown voltage of 4H-SiC JBS diode is also to the original states.At elevated temperature,there are two mechanisms which lead to the reduction of N_eff at the 4H-SiC/SiO₂ interface.One the one hand,the reverse bias-stress induced hole injection into the 4H-SiC/SiO2 interface.On the one hand,electrons at the 4H-SiC/SiO2interface can be emitted into the 4H-SiC body induced by reverse-bias stress at elevated temperature.Finally,the structural optimization and verification experiments of 4H-SiC JBS diode are done.An improved device design that can effectively suppress the electrical parameter drift induced by HTRB is proposed and stripped by using Sentaurus TCAD device simulations software.The results show that reducing the ring spacing and increasing the number of FLRs can lower the sensitivity of 4H-SiC JBS diodes terminated non-equidistance FLRs on effective interface charges without increasing the difficulty of manufacture.The HTRB test results show that the breakdown voltage of optimized 4H-SiC JBS keep unchanged during the stress time when a reverse-bias of 1000V is applied to the optimized 4H-SiC JBS at room temperature and elevated temperature.