Research And FPGA Implementation Of Digital Channelization In Wireless Receiver

The electronic warfare in the environment of complex electromagnetic plays a key role in the modern battleground,and as the most important device in the electronic countermeasure systems,the receivers have been an issue of research.At the same time,they experienced evolutions from analog one to digital one,from conventional one to channelized one.Digital channelized receivers have the advantages of digital one and channelized one,their characteristics are mainly reflected in the bandwidth,large dynamic range and the ability to process multiple signals in parallel.Therefore,digital channelized receivers are able to meet the needs of modern information warfare.Recently,the highly anticipated system-on-a-chip has gradually hold the dominant position due to its characteristic of combining software with hardware,and the platform of the design is a kind of SoC.This paper is about the research of strategy and structures of digital channelized receivers,and the efficient structures of digital channelization based on polyphaser DFT are deduced,which are corresponding to various application scenarios.At the same time,the issues of blindness of channel coverage,ambiguity of adjacent channel,channel-cross of large bandwidth signal have been studied,which may exist in the structure of digital channelization.As a part of the wideband digital receiver,this paper completed the design and implementation of digital channelization consisting of 256 subchannels and 64-channel digital downconverter based on the digital channelization.It mainly includes the modules of digital channelization,channel selector,complex frequency mixer,decimation and FIR filter.According to the different requirements,each parallel DDC can also select 8 kind of bandwidths corresponding to 7 different data decimation factors as its output.At the same time,the FIR filter has been designed with 4 more refined filtering ranges for each output bandwidth,based on the frequency position of the signal.These 4 kind of filtering ranges are defined as BW/2+BW/8,BW/2+2BW/8,BW/2+3BW/8,and BW/2+4BW/8,which the BW here means 7 kind of output bandwidths.The chip used in this design is the Xilinx Zynq XC7Z020,and the conversion speed of ADC and system clock are both 102.4 MHz.For the entire receiver system,Zynq solved the problem of data and instruction interactions between the host computer(PC)and the slave computer(ARM,FPGA).For the DDC involved in this paper,Zynq provides rich and highly integrated logic resources,which makes the entire design has obvious advantages in terms of resource utilization,reliability,and performance.The range of the DDC digital IF filter shape factor in this design is 1.23 ~ 1.48,which has met the design criteria.