The Fast Implementation Method Of BCH Coding And Decoding

NAND Flash is a nonvolatile memory with high density of storage, because of its fast writing and erasing speed, it is widely used in a variety of electronic products and other storage devices. NAND Flash architecture has developed from SLC to MLC, and even TLC, whose manufacturing process has developed to 25 nm and even 20 nm with the fact that the probability of random errors in the NAND Flash is growing. Therefore, the NAND Flash device needs a stronger error correcting capability of ECC algorithms. BCH code has a strong error correction capability and can meet the requirement of NAND flash.In order to adapt to the NAND flash whose Interface are 8 bits,BCH code need the word throttle input and output of the encoding and decoding algorithm.The basic properties of finite fields, the relationship between generator matrix and parity check matrix, the minimum code distance and the basic concepts of weight spectrum are introduced first. Then the BCH coding algorithm whose interface is Monobit is introduced, and then the BCH coding algorithm whose interface is 8 bit is proposed which involves so many matrix operations that it is difficult to implement. In order to meet the requirements of the clock frequency and the design requirements,the BCH coding algorithm whose interface is 8bit is proposed, which can also be named the parallel algorithm of BCH coding.After the parallel coding algorithm is proposed, the decoding algorithm of BCH code is studied which includes three processes: the adjoint calculation, the error position polynomial solution, the Chien search. The classical adjoint polynomial algorithm and Chien algorithm were serial which can meet the requirements of clock frequency with the defect that its data processing rate is slow, so the 8 bit parallel algorithm structure is put forward based on the serial algorithm, which greatly improves the data processing speed. By studying the error position polynomial solution algorithms which include BM algorithm, inverse BM algorithm,we find that the two algorithms can be applied to various data formats.Because this paper uses the BCH binary code, so the inverse of the BM algorithm can be improved by the number of iteration by 1/2.According to the traditional way,the adjoint calculation module, the error location polynomial solution module, Chien search module are combined,because no matter at any time only one module is at work. In view of this situation, the structure of the pipeline is introduced in the decoding process, so that in most cases the three modules are at work at the same time, greatly improving the processing speed of the data and achieving a fast parallel BCH decoder design.Finally, the functional simulation and hardware testing of the parallel coding algorithm and the parallel decoding algorithm are carried out, which proves the correctness of the fast parallel BCH coding and decoding algorithm.