Research On The Module Level Verification Platform Of Communication Baseband Chip

With the rapid development of integrated circuit technology and significant increasing of the size and complexity of the chip design, the design defects in circuit design is rising. It requires the verification to be improved. The application area of the chip has also been more and more widely, so the safety of the design is more and more important. The adequacy of the verification is becoming more and more important to avoid serious consequence caused by the design defects. The chip product updates faster and faster. In the front design flow of large-scale integrated circuit development, the verification costs about 70% time of the whole IC research. Therefore, design efficient and feasible verification method is very important to the design and application of the chip.The design of communication baseband chip module level verification platform in the design of digital integrated circuit technology has been studied in this paper. Based on the OVM verification methodology, we use the System Verilog programing language to design verification platform with high reusability, high reliability, and functional modular. The structure of the Module TB has been improved in this paper. According to the actual function, we divide it into three parts: top_env, src_env and fmt_env. The verification platform also makes the SUB TB instantiated all the traceport interface signal and connect them to DUT(Design Under Test). By comparing the results of the monitor and the scoreboard, we verify that the module is working properly in the entire Debug&Trace system. Different from the previous methods( different traceport have their own TB to verify their own functions), all of these works are completed under the same TB.This simplifies the structure of the TB and completes the series of work of the module level.Eventually,through a specific trace, RFIF, we improved that the verification method in this paper has made a contribution to shorten the verification time, the full coverage of the functional coverage test point, and the reusability, flexibility and stability of the Verification platform.In the last part of this paper, in the Debug&Trace system environment, we use the Makefile configuration file based verification method for RFIF verification simulation. By analysing the simulation results,the simulation time of the new method was 11443 ns, which was significantly shorter than that of the previous 17042 ns, and the function coverage rate reached 100%, we proved that the method is effective and achieves the design index.