Research On Data Compression Caching System Based On FPGA

With the rapid development of mobile internet, how to store the massive user data effectively has been a serious problem. Compress storage uses the highly efficient compression algo-rithms to compress the data, reducing the actual storage space greatly. It also keeps the data integrated using the reverse decompression algorithms to restore the data when the users need to access data. General higher compression algorithm compression rate is very low, so it needs to accelerate the relative hardware to meet the actual needs. The analysis revealed a high compression algorithm needs to store more information in the middle of history in or-der to maintain a high compression ratio. The resources on the FPGA (Field Programmable Gate Array) chip hardware platform are limited and the difference of the external memory and the on-chip memory is large, so we contact the computer system cache (high-speed memory) design experience to realize a hardware-based FPGA hardware Caching system to improve system.This paper analyzes the development of existing Cache technology and the realized prin-ciple, which aims at the FPGA hardware acceleration platforms, extending and improving the frameworks and structures of the Cache in hardware and designs the new organization mapped Caching system. At the same time, the paper is creatively put forward a concept of the Caching system map and data table, which separate the control information and data information storage,Accelerate judgment of the address lookup hit and achieve an easy and efficient hardware cache data replacement algorithm. The concept uses pipelining technol-ogy to accelerate in the internal Caching system module through pre-processing technology, which calculating the memory access address in advance and send it to the memory con-troller continuously so that to maintain DDR is always in full working condition. In addi-tion, the technology designs dynamic Adaptable cache structure, dynamically adapting and extending more specific implementations based on different external memory. Ultimately enhance the performance of the hardware compression system.This paper analyzes the main bottlenecks in Caching system implementation process through analyzes the algorithms address generation mode and the read and write latencies, rearrang-ing combinations fetch address. Minimize address access data delay as much as possible through the adjustment of the buffer temporary address. After studying the impact factor of the buffer cache hit, minimize the number of the access address by adjusting the buffer cache hit ratio space size. In this way, improve the performance and scalability of the Caching sys- tern by using the hybrid storage.In this paper, the final design is completed with the hardware Caching system realization structure and the effect is significant. It uses synchronous clock, which system clock fre-quency is 200Mhz, reducing system time-consuming on average 4.5 times after the actual test work. The highest throughput of the single implementation is 5.66MB/s, compression performance is 4.51 times than the normal software. The Caching system uses less hard-ware and software resources in the implementation, which has a more widely applicability. In addition, the interface of the system has high scalability and can be adapted to the various needs of storage acceleration systems, which has good prospects.