Research And Implementation On Synchronization Technology Of Multi-rate Receiver

Based on the national defense basic project, this paper studies the principles of carrier synchronization, rate adjustment and timing synchronization technology in multi-rate receiver. Through the analysis of realization methods of these modules, the paper designs the system scheme, completes the Matlab simulation and hardware test with FPGA.It also researches the coherent demodulation principle with Costas carrier synchronization that includes DDS and loop filter, on the basic of analysis and contrast on various implementation ways of carrier synchronization. Malab simulation and performance test are also done in this paper.Through analyzing the relation between sampling rate and symbol rate and the high data rate's influence on system process difficulty, the paper studies the implementation method of rate adjustment, sets up the Simulink structure and does test on it.About timing synchronization, it studies the principle of Gardner algorithm, which is composed of interpolation filter, error detector, NCO and loop filter. Through Matlab simulation it finds that Gaussian white noise poses greater influence on timing synchronization than symbol delay. To settle timing jitter that exits in timing loop, the paper innovatively puts forth a measure that adding pre-filter and loop coeffient module in the system. Simulation results demonstrate that this improved method can decrease timing jitter effectively.Based upon the research above, the paper writes the codes with Verilog, does Modelsim simulation and accomplishes hardware test in Virtex-4 platform. Test results indicates that the multi-rate receiver can demodulate the PSK with 1Mbps~5Mbps symbol rate under the channel situation that signal to noise ratio is 10 d B, carrier frequency offset is 100 KHz and symbol time delay is 3 symbol cycle.