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Fpga Hardware Architecture Design And Implementation Of High Speed Data Playback System

Posted on:2017-04-06Degree:MasterType:Thesis
Country:ChinaCandidate:J C ZhuFull Text:PDF
GTID:2348330482472575Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
In the field of signal processing, high-speed data playback system has a wide range of application. It can be used not only as a waveform generator, but also to simulate the real environment. High-speed data playback system plays a vital role when it comes to some environments that are difficult to reproduce.In this thesis, a FPGA hardware architecture is designed based on the FPGA based high-speed data playback circuit. The FPGA architecture control the circuit effectively and realizes two operating modes, which are transmission mode and playback mode. For the transmission mode, FPGA receives massive data from the host computer via a USB3.0 interface. Then the data will be stored in the FLASH array whose size is 128Gb. The total transfer rate can be up to 700Mb/s. For the playback mode, FPGA can read data from the FLASH array and send them to the DAC module. The digital data will be converted to analog signals. Finally the system outputs RF signal after IQ quadrature-modulation chip modulates the analog signal (The playback rate is 500Msps). Meanwhile, in order to optimize the human-computer interaction, a special PC software is designed which supports for multiple waveforms storage and playback. So the system can simulate a variety of test environments, which expands the scope of application and has a great versatility.The layout of this thesis is as follows. Firstly, the background and related work of data playback system are reviewed. Secondly, the function, specification, hardware solution of the system and the overall framework of FPGA hardware architecture are introduced and three main difficulties of the design are put forward. Thirdly, the FPGA architecture design and implementation of the transmission mode and playback mode is respectively elaborated. Complex logic management and efficient algorithms are proposed to solve the difficulties. Finally, a test environment is set up to test the system. The test results show that the system can work properly and the performance satisfies the requirements.
Keywords/Search Tags:Data playback, FPGA hardware architecture, USB3.0, FLASH, DAC, Host computer
PDF Full Text Request
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