Research And Design Of Two Out Of Three System About Autonomic Machine In CTC

In recent years,high reliability and safety of the station and onboard equipments are required with the rapid development of rail traffic.At the same time,the speed and density of trains increase more and more.A vital computer platform applied to autonomic machines is designed in this thesis since it plays an important role in CTC(Centralized Traffic Control).Redundant technology is a feasible method to improve the reliability and safety of systems in the area of railway according to the definition and index of reliability and safety defined in IEC61508.Meanwhile four kinds of redundant safety structures are introduced which are commonly adopted in the railway industry,"hot-standby","two out of two","double two out of two" and "two out of three".Then the reliability and safety of hot-standby and two out of three are analyzed in this thesis according to the Markov analysis.The conclusion is that the two out of three model is more suitable to build the vital computer platform applied to autonomic machine.Based on the theoretical analysis,the design process about the hardware platform layer,operating system layer and platform software layer from hardware and software aspects in detail is introduced in this thesis.The hardware contains the main control unit based on STM32 and the comparator based on FPGA.The software uses event flag from ?C/OS ? to deal with task synchronization.Meanwhile FPGA adopts FIFO to realize clock synchronization.In this way,it solves the synchronization problem in vital computer.In communication,this thesis chooses the serial port and Ethernet which are redundant to each other to improve the safety of the system according to the current situation of autonomic machine.Moreover,watchdog circuit is applied to improve the reliability and safety of the system.Last but not least,this thesis runs a comprehensive test on the vital computer to verify the availability of the platform.Meanwhile the FTA and Markov analysis are combined to analyze the failure rate of the hardware safety integrity of system.Then a safety improvement plan is proposed to decrease the failure rate of system.One of the two highlights of this thesis is the comparator designed on FPGA so that it is the communication interface,and it has the clock synchronization and vote function as well.In this way,the speed of data processing is boosted.The other one is the event flag which is used to accomplish task synchronization.It is easier to realize the synchronization of three machines in this way than using the semaphore method.