Dynamic Reliability Analysis Of FPGA-based Digital Instrumentation And Control System

Field programmable gate array(FPGA)technology based digital instrumentation and control system(DI&CS)is gradually to replace microprocessor-based DI&CS to improve field control performance and efficiency of NPP,as well as to reduce the costs of equipment development.DICS in NPP based on FPGA has been widely recommended by international and domestic scientific research institutions.And it is successfully in many applications in NPP.As a kind of complex programmable logic device,FPGA has abandoned the operating system and Human-machine Interface(HMI).Through the development and embedded,microprocess and FPGA can be combinated.Therefore,the reliability assesement of FPGA devices not only needs to consider the fault conditions of original failure condition,but also consider the new failure mechanism caused by the integration of large number of electronic devices.The reliability analysis of FPGA devices should be implemented from two aspects,logic design fault and hardware random failure.For the hardware random failure,this thesis uses the Boolean logic Driven Markov Process(BDMP)to evaluate the dynamic reliability of single trip parameter and single channel CANDU SDS1 based on FPGA system by KB3/YAMS software.Evaluation is separated into repairability and irreparablity.Corresponding Cumulative Probability Distribution(CPD)curves can be obtained to derive the failure probability.Sensitivity analysis based on BDMP is proposed and applied to SDS1 based on FPGA which verify the applicability of BDMP Sensitivity analysis.To solve the reliability analysis of logic design problem,Dynamic Flowgraph Methodology(DFM)is used to analyze multi-state and multi-time dynamic analysis by Dymonda software.Two Prime Implicants(PIs)can obtained caused by setting top events.Finally,based on the reliability analysis of FPGA DICS,BDMP and DFM are compared in the convenient of modelling,model description capable and qualitative and quantitative analysis power.A dynamic reliability modeling thought to FPGA based DICS is proposed and scheme to perform BDMP Sensitivity analysis is also proposed.