Sensitive Area Analysis In Integrated Circuit Based On Source-isolation Layout Technique

Technology of spaceflight is one of the most rival and flourish industrys which in relation to economy and scientific research of the state.Nowadays it is also rapidly developing field which represents national technology strength and comprehensive national strength.Along with the development of space technology,electronic equipment is usually used in radiation space environment.The SEE of device in electronic instrument is induced by space radiation,and it may make the electronic instrument failure. Semiconductor material and device is sensitive to space environment.Furtherm--ore along with the technology scaling,the SEE sensitivity of device is increasing,which brings more challenge to the stability of spacecraft.Thus,it is necessary to study the mechanism of SEE and the hardening technology.The basic mitigation technique for SEE is to reduce the charge collection in sensitive node.SEE charge collection is controlled by drift,diffusion and bipolar effect.Therefore eliminating the bipolar effect is the traditional way to mitigate P-hit SET.Source-isolation layout technique can mitigate bipolar effect effectively.This paper introducing the hardening effect of source-isolation layout technique by measureing the sensitive area of standard cell. The hardening effectiveness of source-isolation layout technique is further studied which will change with technology scaling.Finally the source-isolation layout technique is used for SEU hardened technique. The main works and contributions of the dissertation are as follows:1) Based on 180 nm bulk CMOS technology, The hardening effectiveness of source-isolation layout technique is estimated by measuring the sensitive area and the width of SET voaltage Width in standard cell.TCAD mix-mode simulation results show that sensitive area of standard cell with source-isolation layout structure decreases dramatically.2) The hardening effectiveness of source-isolation layout technique which is changing with technology scaling is estimated by measuring the sensitive area and SET voaltage Width of standard cell in normal layout structure and source-isolation layout structure. TCAD mix-mode simulation results reveal that the hardening effectiveness of source-isolation layout technique is weakened,while technology is scaling from 180 nm to 65 nm. This is contributed to that the current gain of parasitic bipolar becomes larger with technology scaling in source-isolation layout. TCAD mix-mode simulation results also reveal that the width of SET voaltage Width becomes wider while the N-well contact distance is increased,becomes shorter while the N-well contact area is increased and becomes wider while temperature is increased. We can strengthen hardening effectiveness of source-isolation layout technique by increasing the N-well contact area.3) For further application, source-isolation layout structure is used in SRAM cell. The hardening effectiveness is also discussed by compareing the sensitive area.The result shows that there is some hardening effectiveness.