| With IC manufacturing technology has entered the UDSM(Ultra Deep Sub-Micron) processes,the chip design capability and technological capacity all has been greatly improved. To meet the complexity of the systematic design and the urgent requirement to be on the market, SoC design method based on IP reuse has become mainstream of IC design. SoC chip’s overall performance.system power and modular design is the complexity of the architecture decided by the internal bus/Therefore the design of on-chip bus system is the key factor of determining SoC design success or fail.The AMBA on-chip bus put out by ARM Corp is one of the industry’s most popular bus standard,widely used in all kinds of designs. AMBA bus specification contains AHB bus and APB bus. After understanding the internal SoC on-chip interconnect bus standard and the AMBA bus protocol sufficiently.bus system used AMBA2.0 AHB-APB architecture is top-down designed,which includes AHB bus arbiter,decoder,APB bridge,DMA controller and DES module. The entire circuit codes with hardware description language Verilog HDL,simulate using the NC-Verilog.finally synthesis/place&route/tape out using TSMC 65nm CMOS library.The on-chip bus system designed in this paper has been verified by tape-out,each indicator can meet the requirements for project. The SoC is a low power,high speed,high performance digital signal process for embedded system,support SIMD operation and float instruction.Also it can reach the highest frequency of 500 MHz,2GMACS,used for communication and image manipulation.The chip is taped out with TSMC65nm GP 1P9M process,reach 7.5 million gates, and the die size is 4.30×4.95mm2, core voltage 1.0V.I/O voltage 2.5V.The design can provide strong support for the design of the next generation. |
