CODEC Circuits Design Of Product Codes In Wireless Communication Systems

Error Control Coding is an essential method in overcoming noise and interference from the channel and improving message’s robustness and reliability. Product codes (PC) is a class of near Shannon limit error control codes. PC codes’ simple structure and excellent error correcting ability could reduce mistakes and ameliorate information quality, thus bringing significant decrease to power consumption and increase to lifetime for communication system with heavy data transmission burden. This dissertation focuses on decoder designing of Product codes in wireless multimedia sensor networks, which could decrease errors and meanwhile meet the requirement of data rates.The main content of this thesis includes:(1) Summary of the backgrounds and current research on Product codes in code construction, delay of encoding operation, decoding algorithms and the potential of applications in wireless sensor networks. (2) Analysis and simplification of the most fundamental and widely used decoding algorithm, Chase iterative decoding algorithm for Product codes, modifies the factors of decoding algorithm and simulate the performance. Simulation results prove that code design for wireless communication systems with Matlab software confirms the code’s fitness to baseband communication system in sensor nodes, i.e., decreases the error bits rate to the level of 10-6 with the Signal Noise Ratio lower than 10dB, and reaches a data rate of 8Mb/s. (3) Architecture Design Analysis of PC codes. The mainly work is to analyze the implementation architecture of encoding algorithm and decoding algorithm. In the encoder design, uses registers to store the data instead of RAM, and proposes a timing reorder algorithm fitted for the system. Compared to traditional solution using RAM, the throughput can be 4 times higher, and delay can be decreased to 80% or more. In the decoder design, using the modified twiddle factor and scalding factor, so in the hardware implementation, multiply operation can be transferred into shift operation which can decreases the hardware consumption and improve clock frequency. Simplify the Euclidean value computation equation which makes the subtract operation and multi square operation change into add and multiply. In the uncertain position locating module, the reusing and partial parallel working scheme is employed, this can makes the architecture simple and meet the timing requirement of system. (4) Circuits design of all modules in the encoder and decoder, including RTL design, function simulation and verification, on the basis of this the FPGA verification and test is finished.The simulation and verification results of the circuits show that, the design of proposed PC code has a correct functionality. Compared to current designs that are suitable for the wireless system, the proposed solution can achieve a higher coding gain in low and high signal to noise ratio. Test results prove that, in the Signal to noise ratio of 8 dB, system bit error rate reaches 10-6, throughput is 8.11 Mbps, this can meet the requirement of system in performance like error correction and throughput. The synthesization result of FPGA shows that, decoder can work at the highest frequency of 102.67MHz, encoder can work at the highest frequency of 204.25MHz, this undoubtedly proves that designed circuits can work at the frequency of system working clock frequency. FPGA test also has verified that the circuits could work in accordance with what function simulations have shown, and fulfill the task of decoding received messages. At the same time, the hardware consumption of design is 70% or even less of the current research works.