Power Balance Of Digital Intermediate Frequency Signal Based On SoC

Software radio technology has been widely used in many communication systems. Because transceiver is effected by external factors, so the output signal’s power of each channel are different,and it is not conducive to subsequent processing. In order to solve this problem, this paper proposes a system based on ZYNQ piece and AD9361 to design digital intermediate frequency signal processing system, the core of this system are: integrated the ARM and FPGA on a SoC, radio frequency agile transceivers AD9361 chip. And the system is a software programmable, so it can receive different parameters of the wireless signal. Without replacing hardware system, the system can complete different signal receiving and processing,in order to improve the quality of the radio frequency modulation signal and fraction of coverage. Automatic gain control circuit can guarantee the transceiver when it received weak signals,its gain will be increased,and when it received strong signals,its gain will be reduced. But as the transceiver’s properties improving, we need more requirement of AGC system. But transceiver can only solve signal overall margin increased/decreased,and can’t realize the amplitude balance of each channel, so in order to achieve better processing results,I need to design IP core to realize power balance of each channel.According to the research topic of "power balance of digital intermediate frequency signal based on SoC", mainly completed the analog-to-digital conversion, digital up/down frequency conversion,automatic gain control, and then design the power balance from two kinds of schemes: frequency domain and time domain. In the frequency domain, the time domain signal by FFT converted into frequency domain signal, and then do the power balance of the corresponding frequency. Because the input signal has large time delay after FFT transform, so data are easy to be lost, and data can not be completely outputted, so there’s not easy to real-time processing of data;In the time domain, design of parallel 16 bandpass filter, integrator and multiplier to realize the signal power balance, effectively solved the problem of the time delay existing in the FFT, and downloaded to the SoC, we can see the graph of signal balance. This paper involves Vivado, Linux and Matlab software programming, and finally realize validation on development board, to test out the results and analyze, and reach the requirement of reservation. The work of this paper has a certain reference value to the rest of thesoftware radio system, and it also has important significance to the development of wireless communication.