The Circuit Design Of The Logic Physical Layer Based On Custom Serial Communication Protocol Stack

The development of internet along with the advent of the big data puts forward higher request to the server ability to process mass data, which result in the increasing demands for efficiency of information interaction between devices in the network. Thus, the research of the efficient high-speed I/O serial bus is an inevitable trend. The Custom Serial Communication Protocol Stack is a high-speed I/O serial bus, mainly used in high-speed data transmission of network. The logic physical layer is the logic part of physical layer in Custom Serial Communication Protocol Stack. Thus, the design of logic physical layer plays an important role in the system architecture of Custom Serial Communication Protocol Stack.Through the requirement analysis and designing summary of the logic physic layer, the paper presents a detailed description of the design and implementation. Firstly, this paper introduces some related technology. Subsequently, this paper describes the whole performance, functionality and structure of the design. Besides, the logic physical layer is divided into transmit section, receiver section and link training and control of the state machine, and a transmit section that prepares outgoing information passed from the Data Link Layer for transmission by the electrical sub-block, and a receiver section that identifies and prepares received information before passing it to the Data Link Layer. Then, the paper focuses on the module implementation process, describes the specific steps of sending and receiving messages. Link training state machine complete the consultation mechanisms of the link through the handshake between device. The entire implementation is finished with Verilog RTL level description languages, the detailed design approach is present through the design flow chart, the diagram of system architecture and block diagrams of each module. Finally, the design completes board testing in the VC707 development platform combining the ISE 14.5, further ensuring the robustness of the logic physical layer. The reference clock is 250Mhz, the data width of 256bits, the master clock reaches 125MHz, to meet the design requirements.The design of logical physical layer has the perfect performance and reliable function, fully meeting the requirements of the Custom Serial Communication Protocol Stack among multiple nodes in the data center.