Design And Verification Of Digital Baseband Receiving Circuits For Bluetooth Low Energy

Bluetooth Low Energy (BLE) has many advantages, such as low complexity, low cost, ultra-low power etc. With these advantages, BLE breaks through the traditional application areas of Bluetooth, and has the prospects for a broader market application. The digital baseband receiving circuits mainly demodulate the underlying data in the data communication of Bluetooth, which is the key point in the Bluetooth hardware development. Therefore, this thesis designs the receiving circuits of digital baseband for BLE, which is characterized by low complexity of structure and less resources etc.On the basis of the established architecture of receiving circuits, this thesis does detailed theoretical analysis and design on the circuits of digital downconversion, image-rejection, phase demodulation, bit synchronization and other main circuits. Then the thesis does the modeling and simulation of Matlab for key circuits, and carries out simulation results of the circuits and the system demodulation performance. Considering the demodulation performance and complexity of the circuits, this thesis gives the design, optimization and analysis on simulation results for key circuits in RTL level. The problems like high complexity and waste of resources of traditional image-rejection and phase-detected circuits are improved in this thesis. By choosing the Low-IF and special phase, this thesis applies the adder and substracter instead of the complicated multiplier which simplifies the circuit architecture. Then, according to the symmetry of phase, the range of data on the traditional phase ROM table decreased from [-Ï€,Ï€] to [0,Ï€/4], which reduces the storage of ROM.Finally, this thesis carries out the FPGA verification and DC synthesis. The results show that under the condition with system clock of 8MHz and signal-to-noise ratio of 10dB, the design of BLE digital baseband receiving circuits can correctly accomplish the function of demodulating the information, and the bit error rate is below 0.1% with a certain ability of demodulation. In addition, the improved image-rejection and phase-detected circuits asve hardware resources by 75.64% and 26.80%respectively, compared with the traditional circuits.