Research Of High Linearity And Low Power Infrared Readout Circuit

Infrared imaging technology has been widely applied in the military, business, industry and other fields. Infrared focal plane array readout circuit is the key part of infrared imaging technology, and its performance plays a key role in the infrared imaging system. The main work of this thesis contains two parts. One is to study the design of infrared readout unit circuit with high linearity and low power. The other is to implement the design of system with 32x32 array readout circuit.Firstly, the pixel, column level readout and output buffer units in the infrared readout unit circuit are improved respectively. For the pixel unit, a new type of structure is proposed to improve the linearity of the output signal of the integrated circuit, in which the cascade and gain bootstrap structure are introduced to the original single ended CTIA structure. The influence of non-linearity induced by switches has been eliminated completely by connecting the line select switches to the left of the sampling capacitors and designing appropriate timing. For the input current in the range of 2nA to 60 nA, the linearity of the output voltage of pixel unit is 99.65%, and the power consumption of single pixel unit is 438.58 nW. For the column readout circuit, a new type slave amplifier has been designed when considering the lower contrast of the infrared image. A voltage detection circuit is introduced in order to significantly reduce the operating current of the slave amplifier. The simulation results show that the minimum power consumption of the improved structure is reduced by 43% comparing to the tradition structure. The linearity of the overall column readout circuit is 99.3%. For the output buffer unit, a two-stage CMOS structure is employed. In the input stage, the complementary folded common source gate structure with NMOS and PMOS in parallel is designed to meet large swings and high gain input. In the output stage, class AB common source push-pull output stage is used to achieve large swings and high linearity output. It has been shown that the linearity of the output buffer is 99.53% and the total power consumption is 15.93 mW by the simulation.Then, a 32x32 array readout circuit system has been designed. Custom method is used to perform the schematic and layout design of the analog circuit. Semi-custom method is used to execute the RTL coding, function simulation, logic synthesis, timing analysis, formal verification, and placement and routing of the digital circuit according to the functional requirements. The whole circuit is designed to integrate the analog and digital parts. The results of functional simulation show that the linearity of the output signal is 99.43%. In this thesis, CSMC 0.5μm mixed signal process is used to carry out the DRC, LVS verification.