The Research And Design Of Universal Processing Engine In Embedded Graphics Processing Unit

Embedded Graphics Processing Unit (EGPU) has become an essential part of high-performance embedded platforms, which include smart phones, PADs and other embedded devices. Efficient graphics and data processing has become the basic requirement of people’s daily life, which needs to be accomplished by EGPU. Numerous applications, such as game scene rendering, HD video processing and parallel computing, have promoted the development of EGPU. And they demand the improvement of processing architecture at the same time. Considering the limit of area and power consumption, the design of EGPU with high performance and limited cost has gradually been a focus of current research field. As the semiconductor manufacturing process goes into Post Moore Era, the cost of integrating more processing units into EGPU to enhance the performance increases sharply. The further research of EGPU processing architecture and algorithm optimizing is the key problem of EGPU research, and it has great value in research and application.This thesis aims at the research and design of EGPU processing unit. Firstly, it introduces the principle and rendering algorithms of computer graphics. And then, it studies the evolvement of GPU and EGPU processing architecture, searching the suitable architecture for embedded platforms. With the above research, we can further understand the role of processing unit in EGPU, and finally design the hardware accelerating unit with a balanced performance and cost.In this thesis, a Universal Processing Engine (UPE) for EGPU is proposed, which can be used in both general-purpose computing and 3D graphics rendering. UPE integrates 2 high-efficient Universal Processors (UPs) together, which work harmoniously under the control of a Universal Processor Controller (UPC). UP contains 4 general Streaming Processors (SPs) and 1 Special Function Unit (SFU) to perform general scientific calculation or graphics shading programs. The main contribution of UPE includes three aspects. Firstly, instruction package and co-issue architecture are used in UPE to fully utilize the hardware and balance the workload of each processing unit dinamicly. Secondly, hierarchical architecture and multi-dimensional parallelism are applied in UPE to achieve higher performance. Finally, flexible bus accessing machenism and memory aichitecture are designed to hide memory accessing and processing latency.The design and implementation of UPE have been completed in this thesis. And its logic synthesis has also been finished. A HDL platform of EGPU, which was developed by our research group in earlier stage, is used to verify UPE’s function and performance. Testbench and DUT are applied as the way of verification, and tools like VCS and Verdi of Synopsys are used. With multi-dimensional parallelism and hierarchical processing architecture, UPE achieves 1 GFLPOS, and has the ability to address nearly 100 million vertices or fragments per second in the peak and 56 million per second in the average at a clock frequency of 200 MHz. Experiment results show that the UPE can complete the tasks of graphics processing and general computing successfully. A 0.18μm technology library is used for timing and power analysis. The area of the proposed UPE is about 27mm2, and its power consumption is approximately 198.228mW. Results demonstrate that the proposed UPE can be used in embedded processing platforms, serving as the processing unit of EGPU to accelerate its processing and create a proper balance between performance and cost.